Sep 29, 2019
03:07 AM
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Sep 29, 2019
03:07 AM
Hello,
I am trying to activate POSIF1 interface on XMC4800E196 to operate with BLDC motor Hall outputs. I would like to utilize P3.8, P3.9 and P3.10 inputs, as it is described in the datasheet table.
My attempts for implementing POSIF1 was based on the thread from Infineon forum "XMC4700 POSIF Hall Pattern Update Problem". Unfortunately, that source code with
a few changes does not work. Even PDBG register does not show any changes on the inputs, although voltage level of Hall signals seems to be correct and XMC_GPIO_GetInput() function
return correct data as well.
Initialization:
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU);
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPH ERAL_CLOCK_POSIF1);
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERI PHERAL_RESET_POSIF1);
POSIF1->PRUNC = POSIF_PRUNC_CRB_Msk | // Clear the Run bit
POSIF_PRUNC_CSM_Msk; // Clear the internal state
POSIF1->MCMC = POSIF_MCMC_MNPC_Msk | // Clear the MultiChannel Update Enable MCMF.MSS
POSIF_MCMC_MPC_Msk; // Set Output to 0x0000
POSIF1->PCONF = ( (0 << POSIF_PCONF_FSEL_Pos) | // Hall Sensor Mode
(1 << POSIF_PCONF_HIDG_Pos) | // No Idle Mode
(1 << POSIF_PCONF_MCUE_Pos) | // MC Pattern Updated via SW
(1 << POSIF_PCONF_INSEL0_Pos) | // H0 (IN0B)
(1 << POSIF_PCONF_INSEL1_Pos) | // H1 (IN1B)
(1 << POSIF_PCONF_INSEL2_Pos) | // H2 (IN2B)
(0 << POSIF_PCONF_DSEL_Pos) | // HSDA for blanking delay
(0 << POSIF_PCONF_SPES_Pos) | // Rising Edge on blanking delay trigger
(3 << POSIF_PCONF_MSETS_Pos) | // MSETD to request MCM shadow transfer
(0 << POSIF_PCONF_MSES_Pos) | // Request MCM shadow transfer on rising edge
(0 << POSIF_PCONF_MSYNS_Pos) | // MCM Shadow Update Sync'd to MSYNCA
(0 << POSIF_PCONF_EWIE_Pos) | // Disable External Wrong Hall Event
(7 << POSIF_PCONF_LPC_Pos)); // Low Pass Filter set to 64 clocks
POSIF1->PFLGE = 0;
POSIF1->PFLGE = ( (1 << POSIF_PFLGE_ECHE_Pos) | // Enable Correct Hall Event (CHE) Interrupt
(0 << POSIF_PFLGE_EWHE_Pos) | // Disable Wrong Hall Event (WHE) Interrupt
(0 << POSIF_PFLGE_CHESEL_Pos) | // CHE uses node 0 (POSIFI0.SR0)
(0 << POSIF_PFLGE_WHESEL_Pos)); // WHE uses node 0 (POSIFI0.SR0)
POSIF1->PRUNS = POSIF_PRUNS_SRB_Msk; // Set module Run bit
NVIC_SetPriority(POSIF1_0_IRQn, 10U);
NVIC_EnableIRQ(POSIF1_0_IRQn);
In the while loop such conditions are checked:
if (POSIF1->PDBG & 0x20){
LED_1_ON;
}
else{
LED_1_OFF;
}
if (POSIF1->PDBG & 0x40){
LED_2_ON;
}
else{
LED_2_OFF;
}
if (POSIF1->PDBG & 0x80){
LED_3_ON;
}
else{
LED_3_OFF;
}
Interrupt function for POSIF1:
void POSIF1_0_IRQHandler(void){
XMC_POSIF_ClearEvent(POSIF1,XMC_POSIF_IRQ_EVENT_CHE);
LED_4_TOGGLE;
}
Thank you in advance for any suggestions.
I am trying to activate POSIF1 interface on XMC4800E196 to operate with BLDC motor Hall outputs. I would like to utilize P3.8, P3.9 and P3.10 inputs, as it is described in the datasheet table.
My attempts for implementing POSIF1 was based on the thread from Infineon forum "XMC4700 POSIF Hall Pattern Update Problem". Unfortunately, that source code with
a few changes does not work. Even PDBG register does not show any changes on the inputs, although voltage level of Hall signals seems to be correct and XMC_GPIO_GetInput() function
return correct data as well.
Initialization:
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU);
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPH ERAL_CLOCK_POSIF1);
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERI PHERAL_RESET_POSIF1);
POSIF1->PRUNC = POSIF_PRUNC_CRB_Msk | // Clear the Run bit
POSIF_PRUNC_CSM_Msk; // Clear the internal state
POSIF1->MCMC = POSIF_MCMC_MNPC_Msk | // Clear the MultiChannel Update Enable MCMF.MSS
POSIF_MCMC_MPC_Msk; // Set Output to 0x0000
POSIF1->PCONF = ( (0 << POSIF_PCONF_FSEL_Pos) | // Hall Sensor Mode
(1 << POSIF_PCONF_HIDG_Pos) | // No Idle Mode
(1 << POSIF_PCONF_MCUE_Pos) | // MC Pattern Updated via SW
(1 << POSIF_PCONF_INSEL0_Pos) | // H0 (IN0B)
(1 << POSIF_PCONF_INSEL1_Pos) | // H1 (IN1B)
(1 << POSIF_PCONF_INSEL2_Pos) | // H2 (IN2B)
(0 << POSIF_PCONF_DSEL_Pos) | // HSDA for blanking delay
(0 << POSIF_PCONF_SPES_Pos) | // Rising Edge on blanking delay trigger
(3 << POSIF_PCONF_MSETS_Pos) | // MSETD to request MCM shadow transfer
(0 << POSIF_PCONF_MSES_Pos) | // Request MCM shadow transfer on rising edge
(0 << POSIF_PCONF_MSYNS_Pos) | // MCM Shadow Update Sync'd to MSYNCA
(0 << POSIF_PCONF_EWIE_Pos) | // Disable External Wrong Hall Event
(7 << POSIF_PCONF_LPC_Pos)); // Low Pass Filter set to 64 clocks
POSIF1->PFLGE = 0;
POSIF1->PFLGE = ( (1 << POSIF_PFLGE_ECHE_Pos) | // Enable Correct Hall Event (CHE) Interrupt
(0 << POSIF_PFLGE_EWHE_Pos) | // Disable Wrong Hall Event (WHE) Interrupt
(0 << POSIF_PFLGE_CHESEL_Pos) | // CHE uses node 0 (POSIFI0.SR0)
(0 << POSIF_PFLGE_WHESEL_Pos)); // WHE uses node 0 (POSIFI0.SR0)
POSIF1->PRUNS = POSIF_PRUNS_SRB_Msk; // Set module Run bit
NVIC_SetPriority(POSIF1_0_IRQn, 10U);
NVIC_EnableIRQ(POSIF1_0_IRQn);
In the while loop such conditions are checked:
if (POSIF1->PDBG & 0x20){
LED_1_ON;
}
else{
LED_1_OFF;
}
if (POSIF1->PDBG & 0x40){
LED_2_ON;
}
else{
LED_2_OFF;
}
if (POSIF1->PDBG & 0x80){
LED_3_ON;
}
else{
LED_3_OFF;
}
Interrupt function for POSIF1:
void POSIF1_0_IRQHandler(void){
XMC_POSIF_ClearEvent(POSIF1,XMC_POSIF_IRQ_EVENT_CHE);
LED_4_TOGGLE;
}
Thank you in advance for any suggestions.
1 Reply
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Oct 01, 2019
06:46 AM
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Oct 01, 2019
06:46 AM