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  1. Per Tasking's ctc_user_guide.pdf, zdata is __near...

    Per Tasking's ctc_user_guide.pdf, zdata is __near data. Near data has to be in the first 16K of a segment.

    Try making a group in the first 16K, and allocate zdata and zbss to that group.
  2. These application notes should help: AP32349 -...

    These application notes should help:

    AP32349 - HSM+ Startup V2.0 - Describes UCB configuration for starting HSM work
    AP32399 - TC3xx Debug Protection with HSM - Describes UCB configuration for...
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    Correct. On TC3xx it's a little easier: you...

    Correct. On TC3xx it's a little easier: you could trigger an LBIST via software, which the startup firmware treats as a cold power-on reset.

    It is possible to erase RAM with the Memory Test Unit....
  4. The COPY UCBs are only used if the corresponding...

    The COPY UCBs are only used if the corresponding ORIG UCB is in an ERRORED confirmation state (i.e., invalid confirmation word).

    HSMCOTP0 and HSMCOTP1 are not copies - pay special attention to the...
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    Sorry, my mistake - RAMIN only applies to Cold...

    Sorry, my mistake - RAMIN only applies to Cold Power-On Resets (power applied) and Warm Power-On Resets (PORST asserted externally). It does not apply to System Reset (i.e., SWRSTREQ) or Application...
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    Check SCU_RSTCON.SW - the default reset type for...

    Check SCU_RSTCON.SW - the default reset type for a software reset is 2 (Application Reset), which will not cause RAM to be cleared. If you change it to 1 (System Reset), you should see what you're...
  7. See page 378: And Table 133 on page 380: each...

    See page 378:

    And Table 133 on page 380: each physical sector is 1 MB.
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    Our GTM expert is pretty convinced it's noise. ...

    Our GTM expert is pretty convinced it's noise. Can you try enabling filtering?

    - Set TIMi_CHx_CTRL.FLT_CNT_FRQ to hopefully match your TIM timebase to keep things easy
    - Set FLT_RE and FLT_FE...
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    If it's happening on non-LVDS pins too, don't...

    If it's happening on non-LVDS pins too, don't worry about P21_LPCR2.

    NEWVAL doesn't stop GPR0 and GPR1 from being overwritten:

    Checking with a GTM expert, but can you try this in the meantime?...
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    I don't see any relevant errata for the GTM, and...

    I don't see any relevant errata for the GTM, and there are many applications doing this sort of thing without trouble.

    P21.2 is a bit tricky though, because it can be an LVDS pad. Just to be...
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    How much jitter is "heavily"? The AURIX TriCore...

    How much jitter is "heavily"? The AURIX TriCore CPU does do some speculative fetching, but in most cases, that only results in ~30 ns of variation. Otherwise, AURIX latency is generally very...
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    Can you be more specific - what is the time base...

    Can you be more specific - what is the time base for the TIM? What values are you reading, for which frequencies? Can you show all the values reported up to and through the frequency switch?
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    For all three questions, the same answer applies:...

    For all three questions, the same answer applies: make a separate hex file for each UCB, or perhaps just one set of UCB data for HSM enabled and another for HSM disabled. If you save the data as a...
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    It's possible as long as you haven't blocked...

    It's possible as long as you haven't blocked access from the TriCore or debugger to those sectors (see PROCONHSMCOTP and SP_PROCONHSMCX0/1).

    Keep in mind that if you erase HSM code and then reset...
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    HSM code must reside in the first 640K of PF0. ...

    HSM code must reside in the first 640K of PF0. It doesn't have to be the full 640K.
  16. Check for release-notes.txt in your installation...

    Check for release-notes.txt in your installation folder: e.g., C:\Infineon\AURIX-Studio-1.4.0\release-notes.txt
  17. A Trap with Class 3 TIN 7 is a Nesting Error...

    A Trap with Class 3 TIN 7 is a Nesting Error (NEST), per the TriCore Architecture Manual. A NEST will happen if CALL/RET and TRAP/RFE get mixed up - i.e., if you did a CALL, but the function ends in...
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    There is no automatic cache coherency on the...

    There is no automatic cache coherency on the AURIX.

    If you need to force CPU writes to occur, use the cache W instructions to force a writeback.

    If you need to force the CPU to re-fetch remote...
  19. Don't forget these often-missed other things that...

    Don't forget these often-missed other things that might access PFLASH, depending on your application:
    - DMA Transaction Control Sets loaded from PFLASH
    - Hardware Security Module's Cortex M3 CPU
  20. Sounds like a configuration problem. Either QSPI...

    Sounds like a configuration problem. Either QSPI or ASCLIN SPI should be fine.
  21. QSPI is generally the first choice of peripheral...

    QSPI is generally the first choice of peripheral for SPI. ASCLIN SPI is limited to a single chip select, doesn't support slave mode, and is a bit less flexible in regard to baud rates and sample...
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    Each CPU has its own BIV register (interrupt...

    Each CPU has its own BIV register (interrupt vector table) and interrupt enable/disable status (ICR.IE).

    Do you have an ISR defined on CPU1? What does CPU1's BIV register with your interrupt...
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    You don't have to do any SMU configuration,...

    You don't have to do any SMU configuration, unless your application has Functional Safety requirements.

    I brought up the SMU because it's important to understand where the reset is coming from. ...
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    How are you configuring RSTCON? What's in...

    How are you configuring RSTCON?
    What's in RSTSTAT after the reset?
    Are you configuring the SMU?
  25. I'm not sure what you mean with Write Signal Path...

    I'm not sure what you mean with Write Signal Path - but all writes outside of DSPR use Store Buffers.
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