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Type: Posts; User: cwunder

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  1. Replies
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    PCON1 is a Core Special Function Registers (CSFR)...

    PCON1 is a Core Special Function Registers (CSFR)

    __mtcr(CPU_PCON1, 1);
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    Hi Saulyss, I would add to Neeraj...

    Hi Saulyss,

    I would add to NeerajSDI comments to observe both the Rx (P15.3) and Tx (P15.2) pins of the TC233. The problem could be on either the PC side or device side or both.

    To ensure you...
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    347

    You need a good quality scope to see this signal...

    You need a good quality scope to see this signal at the pin assuming the fSPB = 100MHz.
    4449
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    Are you sure that is the part? I looked at...

    Are you sure that is the part?

    I looked at the device on my board and it is marked CV5

    Could it be SN74LVC1G07 Single Buffer/Driver With Open-Drain Output?

    4435
  5. Please read section 12.3.2.1 Safety Flip-Flops in...

    Please read section 12.3.2.1 Safety Flip-Flops in the AURIX User's Manual V1.4.0
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    Sorry, my mistake. Looking at the user's...

    Sorry, my mistake.

    Looking at the user's manual there is this statement:
    HWCFG[0,2] pins are configured as inputs with weak pull-up after reset, therefore if pins are left unconnected, it is...
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    188

    You really only have two choices for the pin...

    You really only have two choices for the pin states in Standby mode.

    When entering Standby mode you configure the pad states via the PMSWCR0.TRISTREQ bit. All pads may either be in tristate or...
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    I don't know what mode you are using the QSPI in....

    I don't know what mode you are using the QSPI in. Previously you stated you needed it to be variable based on the data received in the same frame. This requires you to use software to control the...
  9. The user's manual clearly states the LBIST clock...

    The user's manual clearly states the LBIST clock is supplied from the backup clock and must be scaled down for a stable LBIST execution. See the SCU chapter 9-50. Review the LBISTCTRL1.LBISTFREQU...
  10. Generally the TriCore supports a software reset...

    Generally the TriCore supports a software reset via an SFR or via the debugger. The specifics to this depends on the specific TriCore device you are using and your connection.
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    Hello AAA, When changing a UCB you need to...

    Hello AAA,

    When changing a UCB you need to ensure that you have a stable power supply and confirmed the values before you perform a reset. The UCB values are only evaluated after a reset. ...
  12. Depending on how you are using the QSPI with DMA...

    Depending on how you are using the QSPI with DMA you could configure it for short data continuous mode while using the phase transition event (PT!) to control the data flow along with the BACON ...
  13. It needs to be set in code

    It needs to be set in code
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    That's great, I did however forget to say you...

    That's great,

    I did however forget to say you also need to check the status of the CCUCONx.LCK bit. You can only update the SFR if this is equal to 0.
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    The AURIX has a concept of access protection for...

    The AURIX has a concept of access protection for the SFR's. When you want to write to a SFR you need to check the access rights.

    You can find the access terms defined in a table in the user's...
  16. The value of the PMSWSTAT.TRIST bit determines...

    The value of the PMSWSTAT.TRIST bit determines the behavior of the pads.

    When you have HWCFG[6] = 0 latched on a Cold PORST this places the pads in tristate mode and any subsequent run-time Warm...
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    I am not sure of your intent, almost all of the...

    I am not sure of your intent, almost all of the SRAM on these devices has ECC so reading uninitialized SRAM is not reliable as the ECC bits associated to that SRAM block are also uninitialized. You...
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    As you stated this is your Transmit interrupt....

    As you stated this is your Transmit interrupt. This can occur in the initialization of the QSPI if you are writing to the TXFIFO, for example writing to the BACON_ENTRY.
    Assuming you don't want this...
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    The CPU0_ICR.PIPN would start with zero. The...

    The CPU0_ICR.PIPN would start with zero. The requirement is that any SRC must be greater than zero for the CPU to vector. Your understanding is basically correct however you can have nested...
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    The CPU will start at level 0 (default) and won't...

    The CPU will start at level 0 (default) and won't initiate an interrupt service. TriCore doesn't have a fixed vector table you can place entries based on their priority (higher the number the greater...
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    At first pass you appear to have everything set...

    At first pass you appear to have everything set correctly. What toolchain are you using?
    If you put a breakpoint on your RX ISR and manually trigger the interrupt (SRCn.SETR = 1) do you go to the...
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    I don't use the iLLD's Concerning the QSPI...

    I don't use the iLLD's

    Concerning the QSPI baudrate for 100 kHz, assuming the fBAUD2 = 200MHz (CCUCON0.BAUD2DIV=1 and fPLL is used for the clock source fSOURCE), then you can set TQ=4, Q=49, A=3,...
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    I would suggest that you download code to the...

    I would suggest that you download code to the PSPR of a core to control the Flash operations (adhere to the principle of locality). This would allow the fasted possible loading of the pages 64-bit...
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    The user's manual has a section with a table (see...

    The user's manual has a section with a table (see section 1.1.2 Device Variants) for the differences. In addition there are also Data Sheet Addendums for the TC22x and TC21x variants.

    Do you have...
  25. The are few ways of which here are two: you...

    The are few ways of which here are two:

    you can use an __attribute__ in the definition


    uint32 __attribute__((section (".data_cpu2"))) myCpu2Data;

    0x50000000 0x50000003 4 g myCpu2Data ...
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