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Type: Posts; User: cwunder

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  1. Thread: TC297 pinout

    by cwunder
    Replies
    1
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    55

    The TC297 is an LFBGA-292 package which is shown...

    The TC297 is an LFBGA-292 package which is shown in the datasheet.

    If you are looking for a coloring like what is shown in the above picture you can review Figure 22 in the application note...
  2. The SCU is the System Control Unit and controls...

    The SCU is the System Control Unit and controls the a lot of the device system behavior that also includes the Power Management System (which has its own chapter in the user's manual). The SCR is...
  3. Thread: SysTick

    by cwunder
    Replies
    3
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    153

    As Markus states the functionality could be the...

    As Markus states the functionality could be the same however the implementation is different. The XMC is a 24-bit down counter however with AURIX it is free running 64-bit counter. With AURIX you...
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    RWW is supported between Program and Data Flash....

    RWW is supported between Program and Data Flash. Concerning Program Flash this is supported only between the different PFLASH banks. The TC39x has 16Mbytes of internal PFlash and supports 6 banks, 5...
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    461

    You will also need to adjust your CAN timing...

    You will also need to adjust your CAN timing since it changed.

    Using 1 CAN node and 16 message objects only requires 12MHz on the fCLC (which is the same for the fSPB) for 1MBaud. You are at...
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    387

    You are not providing enough information to know...

    You are not providing enough information to know what the problem could be that you are experiencing (at least for me)?

    Here is a bifaces code snippet for the TC38x A-Step device. One case is to...
  7. Replies
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    387

    Please have a look to the iLLD example in the...

    Please have a look to the iLLD example in the files IfxCpu_Trap.h and IfxCpu_Trap.c. It would be easiest to have code in the trap table to get the information.


    /** \brief Structure to contain...
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    461

    Your clock settings do not appear to be correct....

    Your clock settings do not appear to be correct. Where did you get the code for configuring the PLL and clock dividers?

    It says you have selected the PLL as the clock source for fsource however...
  9. No, the user is responsible for the correct UCB...

    No, the user is responsible for the correct UCB settings (that are stored in the Data Flash), including that they are in a "Confirmed" state for production. This would prevents any further...
  10. Replies
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    461

    Have you created the QSPI driver? The FPI is...

    Have you created the QSPI driver?

    The FPI is the SPB in this implementation. This can run up to 1/2 the frequency of the SRI (133MHz) on this device.
    The QSPI depends on both the frequency of...
  11. Replies
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    525

    The HSM has the hardware features for the SHE, it...

    The HSM has the hardware features for the SHE, it depends on the software implementation to realize the functionality along with how you use the Data Flash for the Key management. You should discuss...
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    525

    - This device is Medium Evita (since it doesn't...

    - This device is Medium Evita (since it doesn't have an asymmetric HW Crypto Engine), TC3xx supports full Evita
    - SHE HIS is realized with software that runs on the HSM, TC234LP the "P" indicates it...
  13. This is referenced in the "References" section...

    This is referenced in the "References" section [2].
  14. Can you provide more information as to what your...

    Can you provide more information as to what your program does (the behavior) to be able to provide more insight to what issue you are seeing.

    If you set a breakpoint in the "interruptGpt12"...
  15. I am not sure why the context management trap...

    I am not sure why the context management trap would be different on the SCR example.

    Can you provide the information from the "trapWatch" struct? This can help to find out what is going wrong......
  16. The latest iLLD version is v1.0.1.11.0 have you...

    The latest iLLD version is v1.0.1.11.0 have you tried this?

    Have you also just tried a project without the SCR and does this run ok?
  17. Replies
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    364

    What device are you using?

    What device are you using?
  18. Replies
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    381

    Just a caution, in the datasheet the UCB...

    Just a caution, in the datasheet the UCB Retention Time requires that you follow these limits:

    Max. 100 erase/program cycles per UCB, max 500 erase/program cycles for all UCBs together

    Does...
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    The user's manual code only performs one DMA move...

    The user's manual code only performs one DMA move per software request. I see a few issues with your code.

    uint8 source[100] __at(0x70000000) = "I love sunny days";
    uint8 destination[100]...
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    235

    If D105 (V_UC) is not on then you need to look at...

    If D105 (V_UC) is not on then you need to look at the power supply. First check the voltage at the MPS (TM) pin 22 on the power supply (TLF35584QV). If this is low then the watchdog is enabled and if...
  21. Have you reviewed section 3.1.1.4 Stand-by...

    Have you reviewed section 3.1.1.4 Stand-by controller handling during start-up?

    The start-up procedure will initialize stand-by controller (SCR) RAMs and trigger SCR boot when the last reset:
    • ...
  22. I don't see any issues using PLS UDE to debug...

    I don't see any issues using PLS UDE to debug with the ADS created elf file.

    4728
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    The other cores need to be initialized by a core...

    The other cores need to be initialized by a core that is already running before that core is enabled so you need some software somewhere.

    Are you usings ADS?
    Then you can have a look to the file...
  24. Yes it is available for everyone except the SCR...

    Yes it is available for everyone except the SCR as you have disabled it.
  25. Replies
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    302

    The LA-7756 supports both JTAG and DAP. How are...

    The LA-7756 supports both JTAG and DAP. How are you connecting via the Tantino?

    This is what I use (w/JTAG):

    SYStem.CPU TC1782
    SYStem.CONFIG CORE 1. 1.
    SYStem.Option.RESetBehavior Halt...
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