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Type: Posts; User: Neal Manson

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  1. Have you looked at the SafeTlib demo application?...

    Have you looked at the SafeTlib demo application? See 01_SafeTlib/application/src/RefApp.c, and the TresOs configuration (e.g., 01_SafeTlib/Application/cfg/RefApp_Cfg_234.zip).

    Regards,
    Neal
  2. Hi Robbie. The TriBoard's USB interface connects...

    Hi Robbie. The TriBoard's USB interface connects to the AURIX DAP debug port, and also gives the PC a virtual COM port connected to ASCLIN0 on the AURIX.

    Install a terminal emulator (Tera Term,...
  3. Thread: AURduino

    by Neal Manson
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    3,762

    AURduino

    http://www.hitex.co.uk/index.php?id=3650

    New Arduino form factor TC275 board from Hitex. Neat!
  4. Hello Federico. Have you enabled the FCE...

    Hello Federico. Have you enabled the FCE peripheral first? Most peripherals are disabled by default. Any attempt to write to a peripheral register where the peripheral is disabled (other than the CLC...
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    By default, the CPU is in supervisor mode...

    By default, the CPU is in supervisor mode (PSW.IO=2), and OVCCON access is enabled (SCU_ACCEN0 = 0xFFFFFFFF). If you're in user mode (PSW.IO=0 or 1), or SCU_ACCEN0 has been changed, you'll need to...
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    Try this instead: // invalidate all data...

    Try this instead:

    // invalidate all data caches
    OVCCON.U = 0x00040007; // DCINVAL = 1, CSEL2=1, CSEL1=1, CSEL0=1

    // invalidate program cache
    PCON1.B.PCINV = 1;

    // invalidate program line...
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    See UCB_DFlash in the User Manual, and...

    See UCB_DFlash in the User Manual, and PROCOND.RAMIN/RAMINSEL. With the default values, all of RAM is initialized on a warm power-on reset (i.e., your external watchdog asserts PORST).

    It sounds...
  8. You can't span banks with a single write command....

    You can't span banks with a single write command.

    For optimal speed, you should be using 256 byte packets. Since 2 MB is evenly divisible by 256 (unlike 192), you then wouldn't have the issue of...
  9. If you've shorted Tx and Rx together, then there...

    If you've shorted Tx and Rx together, then there won't be an ACK, and the TEC will not increment past the passive error limit of 128, per this part of the CAN spec:
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    The most likely cause is a watchdog timeout. ...

    The most likely cause is a watchdog timeout.

    Have you checked the value of TRAPSTAT after the NMI occurs?

    If TRAPSTAT.SMUT is set, what are the SMU alarm register values (SMU_AG0...SMU_AG6)?
  11. Make sure at least one boot mode header is set: ...

    Make sure at least one boot mode header is set:

    Properties / C/C++ Build / Memory / Boot Mode Headers
    Boot Mode Header configuration: Generate Boot Mode Header
    Hardware configuration start-up...
  12. Both addresses actually refer to the same program...

    Both addresses actually refer to the same program flash bank - see Table 4-2 in the TC27x User Manual. The difference is that 0x80xxxxxx is cached, but 0xA0xxxxxx is not.

    PF0 occupies from...
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    The latest version supports the TC23x. ...

    The latest version supports the TC23x.



    http://free-entry-toolchain.hightec-rt.com/
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    I suppose you could set ICR.CCPN to 255. But...

    I suppose you could set ICR.CCPN to 255. But ENABLE and DISABLE are the customary method.
  15. Hi Kuldeep. Each write must start at an address...

    Hi Kuldeep. Each write must start at an address that is aligned to a 32-byte boundary. You can't write less than that - you'll have to pad your data to meet the next boundary.

    You used the phrase...
  16. The TC234 doesn't have the Flexible CRC Engine,...

    The TC234 doesn't have the Flexible CRC Engine, but it does have the CRC32 instruction, and the CRC32 used by the DMA engine. Here's some sample code that calculates the CRC32 of 0xA0018000 through...
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    Mostly correct - except that CPU1 also has a...

    Mostly correct - except that CPU1 also has a lockstep core. That's part of the safety concept, and there's no impact on performance.

    Conceptually true, but the TC29x is a little more complicated -...
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    The TC29x has three available cores. This...

    The TC29x has three available cores.

    This excerpt from TriCore Architecture Manual Vol1 explains the term TriCore:


    This excerpt from the AURIX Safety Manual explains lockstep core operation:
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    I doubt the simulator has changed in a long time....

    I doubt the simulator has changed in a long time.

    Your example doesn't tell the whole story though - can you include all of the declarations and definitions necessary for the single line of code...
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    Works fine for me with Tasking v4.3r3 - that is,...

    Works fine for me with Tasking v4.3r3 - that is, x is 0x070204:



    Could you show how you're actually invoking the macro?
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    It doesn't sound like anything too complex to...

    It doesn't sound like anything too complex to throw off the simulator, but let's see the specifics.
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    Looks like some parentheses are mismatched, and...

    Looks like some parentheses are mismatched, and some are missing. Try this instead:

    ((a&0xFFFF) << 16) | ((b&0xFF) << 8) | (c&0xFF)

    If there's still trouble, post the full macro definition.
  23. Two roadblocks left: First, your address is...

    Two roadblocks left:

    First, your address is still within the first 8K of RAM, which is used by the BootROM. Move your non_volatile block somewhere out of the first 0x2000 bytes.

    Second, unless...
  24. I don't see any definition for non_volatile in...

    I don't see any definition for non_volatile in your linker file.

    Here's an example that should help. This example is based on the TC23x:

    C file:

    LSL file:

    You can verify that the...
  25. Your thinking is basically correct. Each checker...

    Your thinking is basically correct. Each checker cores is tied to its master core - you cannot program the checker cores independently. A TC27x has a CPU0 with lockstep, a CPU1 with lockstep, and a...
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