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  1. Hi Nasrine. Is *all* of the code in PSPR? Is...

    Hi Nasrine. Is *all* of the code in PSPR?

    Is the local stack in DSPR, or dLMU?
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    This looks like crosstalk between channels,...

    This looks like crosstalk between channels, obscured by using a digital sampler instead of an analog scope.

    Do you have a tool to look at the signals in the analog domain? You're probably getting...
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    This usually points to watchdog trouble. By...

    This usually points to watchdog trouble. By default, having a debugger connected disables the watchdog system. You can change this behavior in Trace32 with SYStem.WDTSUS.
  4. The NBTR0.NISO bit (bit 15) is described in the...

    The NBTR0.NISO bit (bit 15) is described in the errata sheet. The default is 0 (ISO 11898-1:2015), but it can be changed to 1 (DIS 2014, non-ISO).
  5. The STM doesn't generate periodic interrupts...

    The STM doesn't generate periodic interrupts (except for overflow). In your STM IRQ handler, you need to set the STM up for the next period. Try this:


    IFX_INTERRUPT(stm0_isr, 0, 2)
    {
    ...
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    You'll need a MyICP account for the BSDL files,...

    You'll need a MyICP account for the BSDL files, and the account needs to be promoted to have access to TC3xx documentation.

    Here's a direct link:...
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    Every operating system I've seen uses the STM,...

    Every operating system I've seen uses the STM, but you certainly could use the GTM instead.

    There aren't any hardware safety mechanisms that cover the STM or the GTM.
  8. UCB_DBG for sure. UCB_PFLASH is another layer on...

    UCB_DBG for sure. UCB_PFLASH is another layer on top of that, and I don't see that used often on the Americas side of the Atlantic, for what it's worth.

    If you're using the HSM, you also need to...
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    All the STMs are fed by the same clock source...

    All the STMs are fed by the same clock source (divider set by CCUCON0.STMDIV), so they shouldn't diverge. They're all enabled by default, but I'm not sure where they're started within the internal...
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    When you're reading A0004000, is it simply...

    When you're reading A0004000, is it simply erased, or did you program 0s into it? If you try to load a value from erased PFLASH, you'll get a CPU trap (Data Synchronous Error).

    Some debuggers are...
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    Under normal circumstances, no - they're driven...

    Under normal circumstances, no - they're driven by the same clock, so the delta will remain constant. But it's possible (albeit unlikely) for one to be corrupted by a soft error (bit flip).
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    No, ADS does not support compiling or assembling...

    No, ADS does not support compiling or assembling for the MCS.
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    Are you building with --eabi=+float? If not,...

    Are you building with --eabi=+float? If not, it's going to have to use software emulation for double variables, and that will be slow.

    Could it be that your compiler flags include both...
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    The XMC4400's HRPWM has some tricks that the...

    The XMC4400's HRPWM has some tricks that the AURIX doesn't:

    Although the TC3xx GTM fast clusters can run a PWM with 5 ns resolution, that doesn't approach the 150 ps resolution of the XMC.
  15. The traditional standalone debuggers are iSYSTEM,...

    The traditional standalone debuggers are iSYSTEM, Lauterbach, and PLS.
  16. I'm not sure what debugger you're using, but you...

    I'm not sure what debugger you're using, but you can force the PC register to be somewhere else. In iSYSTEM for example, you can right-click on an instruction and "goto".
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    How many times have you flashed PFLASH and/or the...

    How many times have you flashed PFLASH and/or the UCBs? The datasheet specifies the maximum number of program/erase cycles.
  18. No, but it depends. Let's say you have three...

    No, but it depends. Let's say you have three cores that are setting or clearing a bit in a 32-bit variable - then you'd need some sort of semaphore or atomic instruction.

    By default, the dLMU and...
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    According to this page, TriCore is not a...

    According to this page, TriCore is not a supported architecture.
    https://nuttx.apache.org/docs/latest/introduction/supported_platforms.html
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    That's correct by default, but it depends how you...

    That's correct by default, but it depends how you have the triggering set up. Each EVADC group arbitrates between its three queues, and you can change the relative priorities to meet your...
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    Each converter (e.g., G0 and G8) arbitrates...

    Each converter (e.g., G0 and G8) arbitrates between three request queues. For the example you gave, each converter will do three conversions serially, with G0 and G8 working at the same time.
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    Try using the micro USB connector on the TriBoard...

    Try using the micro USB connector on the TriBoard with Memtool. If that works, then you've got trouble with the JTAG cable, or the Lauterbach configuration.
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    Here is a little example of overlay. I wrote it...

    Here is a little example of overlay. I wrote it for a TC27x, so it's using OVC2 (CPU2 overlay registers) instead of OVC0, and it remaps PFLASH access to LMU RAM, so you'll need to adapt the...
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    Possibly important to note that using DMA isn't...

    Possibly important to note that using DMA isn't really faster, because there's a bit of overhead in arbitrating between DMA channels and swapping transaction sets in and out. A good general...
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    The GTM is pretty slow on the SPB. Is...

    The GTM is pretty slow on the SPB. Is PeriodArray in local DSPR? That will only help a tiny bit.

    You could make a gigantic DMA linked list to do the transfers from PeriodArray into...
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