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Type: Posts; User: EbbeSand

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    Dear Forum-Member,

    i have a problem by receive data over dual port spi, transmit is all ready done,


    //SCLK configuration 5.2
    const XMC_GPIO_CONFIG_t...
  2. Again, my answer is yes and RTFM sorry that I...

    Again, my answer is yes and RTFM sorry that I send this question to you


    An the answer is max. Fequency 30 MHz !!

    Please correct me if I am wrong or if you are nice you confirm my...
  3. XMC4700 SPI configuration --> QSPI Maximum Bautrate

    Hello Forum Member,

    To simplify I have left the remaining settings

    const XMC_SPI_CH_CONFIG_t SPI_U2C1_config =
  4. Hi Jesus, Sometimes things can be so easy that...

    Hi Jesus,

    Sometimes things can be so easy that you can believe it. But now for your question yes it works.
    Thanks for your help and a successful week.

    Best regards

    Ebbe Sand
  5. XMC4700 SPI configuration --> SCLK = 8 KHz

    Good Morning Forum Member,

    I want to generate a SCLK frequence of 8 kHz, by SPI I can said that this is equal tp 8 kbit/s correct?

    now I have the problem which baudrate (nummeric value) is...
  6. Hi Query1920, sorry for the slow Response on...

    Hi Query1920,

    sorry for the slow Response on your question, but I did't saw that you send me a question on my post

    yes the EBU Interface is running

    For the Adressing I use the following...
  7. Question about RTC registers are mirrored in SCU

    Dear Forum Member


    Can I assume that the RTC will update the mirror register in the SCU block. And I can check via the SCU or its register when an update has taken place.

    After the...
  8. Sorry *****RTFM****** The RTC module is a...

    Sorry *****RTFM******

    The RTC module is a part of SCU from programmming model perepcetive and shares
    register address space for configuration with other sub-modulesof SCU. RTC registers
  9. XMC47 1.RTC-SCU transfer Speed over serial interface & 2. Synch with 1Hz ext. Signal

    Dear all Member,


    1.) RTC-SCU-CPU-SRAM Transfer Speed over Serial Interface

    Above Picture was taken from Reference Manual. Unfortunately I can't find a hint in the Manual how fast I...
  10. Now I have another Problem Can it happen that...

    Now I have another Problem

    Can it happen that my Slow EBU interface to the LCD slows down my AHB bridge in the XMC there or the EBU register is run over.

  11. Look in a newer thread ...

    Look in a newer thread

    Ebbe Sand
  12. Hello Jesus, So I have to go into the...

    Hello Jesus,

    So I have to go into the configuration structure for the values ​​from the CTLL
    Register the register (called uint32_t control in the structure) with the same values ​​as those in...
  13. GPDMA configuration with XMC Lib functrions (XMC4700)

    Dear forum members,

    I Need your help,

    In a single block transfer, I can use the following procedure when configuring my DMA channel

    1.) Fill structure XMC_DMA_CH_CONFIG_t
  14. Hello Michael I use maximal Full Speed for the...

    Hello Michael

    I use maximal Full Speed for the USB Interface
    An therefore my question If I config the Interface to Full Speed Master the USB-IP set the pull
    down on the D+ and D- line in...
  15. Replies

    Question about DUAL - SPI Mode

    Hello Forum,

    It is possible that I can uns a USIC Interface in this matter that the SPI Master is send
    16 clocks, and read the 16 Bit from two slave into the Input Register of the XMC.

  16. USB XMC4700 use as Host (pull-down are active in host mode?)

    Unfortunately, I can only guess the switch-on of the pull-downs in host mode implicitly from the data sheet.
    According the USB physical layer specification, I know a 15kohm pull down must be...
  17. So I think I found my mistake and now understood...

    So I think I found my mistake and now understood at what points in the data sheet are importent for answer my question

    pll base frequency
    Without a clock Input fOSC, the PLL gradually slows...
  18. Possibly written too complicated In the Manual...

    Possibly written too complicated

    In the Manual the Maximum base PLL fequency is 140 MHz. (see Picture)


    Why then, in most examples, are PLL operated at 288 or 144 MHz?

    Table 11-5...
  19. PLL Frequency Maximum? --> Datasheet vs. system_XMC4700.c

    Hello forum members and all of you first a nice St. Nicholas day.

    The below command is out from the above mentioned c-file

  20. Configuration of DMA for Transfer vom RAM to EBU Interface on XMC4700

    Good Morning Everyone,

    currently I try to config the DMA Channel for transfer 240x320 unit16_t values
    from a Frame buffer in my RAM to the EBU Interface. But with the current
    configuration and...
  21. Replies

    Cirrus Logic USB Core in XMC4700

    Hello Everybody

    I hear that a Cirrus Logic USB Core was implemented in XMC Series.
    Can someone confirm that? And if answer yes which core are implemented?
    If the answer no, maybe someone knows...
  22. Replies

    Hello Jesus, thanks for your help now the...

    Hello Jesus,

    thanks for your help now the Interrupt is fired

    Best regards

  23. Replies

    ERU to GPIO P0.6 on XMC4700

    Hello I use the following initialisation

    XMC_ERU_ETL_CONFIG_t wsync_event_gen_config =
    .source = XMC_ERU_ETL_SOURCE_B,
    .input = ERU0_ETL3_INPUTB_P0_6,
    .edge_detection =...
  24. EBU 16-Bit on XMC4700 with CD on A19 (16 BIT EBU on XMC4500 runs well)

    Hello I try to start the 16 Bit EBU on my new XMC4700 board

    // EBU - address pins
    #define EBU_AD0 P0_2
    #define EBU_AD1 P0_3
    #define EBU_AD2 P0_4
    #define EBU_AD3 P0_5
    #define EBU_AD4 P3_5
  25. Question about SRAM declaration at XMC4700

    Short question I work with a XMC4700 board
    Overall, the controller has 352 Kbytes SRAM

    from data sheet:

    PSRAM 1FFE 8000-1FFF FFFF hex 96 KByte
    DSRAM 2000 0000-2001 FFFF hex 128 KByte
Results 1 to 25 of 32
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