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  1. This usually doesn't work out - you're generally...

    This usually doesn't work out - you're generally better off using the PMU Verify Erased commands to detect erased memory.

    Reading from erased PFLASH swamps the ECC algorithm, which means it...
  2. The intention is to signal an...

    The intention is to signal an application-specific software fault. Perhaps a parameter outside of the allowed range, an invalid state in a state machine, a hardware input out of range, etc.
  3. Wait wait the WDTCPU registers are at 0xFxxxxxxx...

    Wait wait the WDTCPU registers are at 0xFxxxxxxx too (e.g., SCU_WDTCPU0CON0 at 0xF0036100).

    What if you write to an unrestricted register like P00_OUT (0xF003A000)? Does that also fail?
  4. Oops - per 15.3.1.7 SMU_core State Machine, the...

    Oops - per 15.3.1.7 SMU_core State Machine, the RUN->FAULT transition only occurs if the FSP is asserted for an alarm. So ACNT increasing but FCNT remaining at 0 is expected in this case, if...
  5. Please share your configuration for SMU_AG10CF0,...

    Please share your configuration for SMU_AG10CF0, SMU_AG10CF1, SMU_AG10CF2, and SMU_AEX.



    I do not recommend using alarms as part of normal software execution. Software alarms have the same...
  6. Bus error.

    Bus error.
  7. Using an SMU alarm to indicate normal...

    Using an SMU alarm to indicate normal functionality strikes me as a bad idea. You'll have to keep switching the SMU from FAULT state back to RUN.

    What is it you're trying to accomplish with...
  8. Correct: because of the dividers, not all errors...

    Correct: because of the dividers, not all errors will be caught. That is one reason the Safety Manual lists 3.3.4 External Time-Window Watchdog as a Top Level Safety Requirement.
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    Sorry, I should have been clearer - Infineon's...

    Sorry, I should have been clearer - Infineon's MCAL is not free and requires a license.
  10. Correct. See WDTCPUyCON0 in Table 275: that's...

    Correct. See WDTCPUyCON0 in Table 275: that's what the CPUy means, per Table 3 Access Terms.
  11. The fBACK alarm range test limits in...

    The fBACK alarm range test limits in CCUCON4.UPTHR and LOTHR ensure that both fBACK and fPLL0 are correct.
  12. Do you get the same bus error with COMDATA? If...

    Do you get the same bus error with COMDATA? If so, can you post your telegrams?

    The "E" registers are ENDINIT protected, so you'll either need to go through the unlock sequence - see 9.4.4 The...
  13. It's different on TC2xx. See 7.1.5 Clock...

    It's different on TC2xx. See 7.1.5 Clock Monitors. That's generally handled by the MCAL and tested for latent faults at startup with SafeTlib.
  14. Can you show the project configuration? It seems...

    Can you show the project configuration? It seems like yours might be missing the ResourceM module. Here's what mine looks like:

    4784

    If you're creating a brand new project, people often miss...
  15. See Figure 90 Clock Monitor: - CCUCON3.BACKMONEN...

    See Figure 90 Clock Monitor:
    - CCUCON3.BACKMONEN is a test of whether fBACK is running at all.
    - CCUCON4.MONEN tests fBACK against a configurable upper and lower limit.
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    Infineon's MCAL is the lowest layer. The MCAL is...

    Infineon's MCAL is the lowest layer. The MCAL is distributed with a free version of Elektrobit's Tresos tool, which lets you configure the MCAL parameters and generate C configuration files.

    The...
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    In the datasheet, under Flash Target Parameters.

    In the datasheet, under Flash Target Parameters.
  18. From previous experiments, I suspect access to...

    From previous experiments, I suspect access to local memories can flicker between CPU access and remote (SRI) access every other cycle (presuming the CPU and SRI are at the same speed).

    Other...
  19. Hi Eric. A write request from the SRI can indeed...

    Hi Eric. A write request from the SRI can indeed stall a CPU that is accessing its own memory.

    Estimating the impact is exquisitely difficult, because you have to factor in the exact sequence of...
  20. Hi Valerie. There's a System Timer (STM) for...

    Hi Valerie. There's a System Timer (STM) for each CPU core. That is typically used to drive an operating system timer (something like 1 ms), but you could use that.

    You can also use the TOM...
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    Is the SMU locked? Check SMU_KEYS.CFGLCK. Once...

    Is the SMU locked? Check SMU_KEYS.CFGLCK. Once the SMU is locked, alarm configuration cannot be changed - see 15.3.1.10.1 Register Write Protection.
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    The way to interpret this is: SMU_AG10FSP =...

    The way to interpret this is:

    SMU_AG10FSP = 0x00030000 => bits 16 and 17
    FSP is asserted for ALM10[16] (Recovery Timer 0)
    FSP is asserted for ALM10[17] (Recovery Timer 1)

    SMU_AG10CF0 =...
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    The SMU reaction to each alarm is configured in...

    The SMU reaction to each alarm is configured in SMU_AGiCFj: see Table 529 SMU Alarm Configuration. The three bits are spread out over the three registers SMU_AGiCF0..2. As an example, to set the...
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    After the reset, SMU_ADx will have a snapshot...

    After the reset, SMU_ADx will have a snapshot from before the reset. That might give you a clue like "SRI bus error", but the details will be lost.

    If you can change the SMU reaction to NMI, your...
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    In general, I only recommend having the SMU...

    In general, I only recommend having the SMU reaction configured to reset for a select few alarms, such as the watchdog recovery timers. Nothing captures the trap cause or PC across a system reset. ...
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