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    If you want to change an output back to GPIO, you...

    If you want to change an output back to GPIO, you can set its IOCR register from an alternate output function (>=1) back to GPIO (0).

    For example, for pin 65 / P15.5:

    P15_IOCR4.B.PC5 = 0x11; ...
  2. It's not only possible, it's mandatory: each core...

    It's not only possible, it's mandatory: each core has its own set of Memory Protection and Safety Memory Protection registers.

    The Memory Protection Unit limits what ranges that particular CPU is...
  3. No, it's not - but it could be that your linker...

    No, it's not - but it could be that your linker file is not handling the PSPR copy correctly.

    Here's a ilttle example that does both CPU Memory Protection and Safety Memory Protection.

    ...
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    Well... TC37x instead of TC27x, but you could...

    Well... TC37x instead of TC27x, but you could just modify the TC39x scripts, and cut memory from 16 MB to 6 MB.
  5. __private is generally used to put a function...

    __private<n> is generally used to put a function in one core's PSPR (Program Scratch Pad) memory. It doesn't prevent another core from calling the function - but if another core does, it will likely...
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    When a debugger is connected, the watchdog system...

    When a debugger is connected, the watchdog system is disabled by default. Could it be that that line just happens to be where the watchdog expires? Which alarm are you seeing?
  7. There is a commercial version of Memtool...

    There is a commercial version of Memtool available from PLS that supports command line scripting.
  8. Yes: see the CPU chapter for details. In...

    Yes: see the CPU chapter for details. In addition to CPU cycle count and CPU instruction count, these counters are also available:

    5198
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    Loads aren't allowed in User-0 mode either:

    Loads aren't allowed in User-0 mode either:
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    Is your code executing in User-0 mode (PSW.IO=0)?...

    Is your code executing in User-0 mode (PSW.IO=0)? User-0 code will invoke an MPP trap or SMU alarm if it accesses the peripheral space.

    If it's not that, what alarm are you getting? What's in...
  11. "Maybe"? It's a bit spammy if you don't provide...

    "Maybe"? It's a bit spammy if you don't provide specific links to solutions that help an FPGA interface with an AURIX microcontroller.
  12. See AP32264 - DXCPL for AURIX. I'm not sure if...

    See AP32264 - DXCPL for AURIX.

    I'm not sure if you're using TC2xx or TC3xx. The primary reference for DAP is in the OCDS spec, which is generally only given to debugger makers (iSYSTEM, PLS,...
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    Is this executing on CPU0? If it's executing on...

    Is this executing on CPU0? If it's executing on a different CPU, could it be that the data cache is active, and the debugger's view of memory is stale?
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    There could be 32, because the CPXE/DPRE/DPWE...

    There could be 32, because the CPXE/DPRE/DPWE registers are 32 bits - but the actual number of data range registers is 18 (DPR0..17_L / DPR0..17_U), and 10 for code range registers (CPR0..9_L /...
  15. After consulting with the TLF35584 expert: -...

    After consulting with the TLF35584 expert:
    - Writing RSYSPCFG0.STBYEN=0 won't help, because it does take effect immediately in WAKE state, which indirectly causes the AURIX to reset:

    - Even if...
  16. Didn't you start by saying you wanted to turn the...

    Didn't you start by saying you wanted to turn the AURIX off? You can either keep the AURIX Standby Controller alive with VEVRSB, or switch it off completely by cutting off all supplies.
  17. Nice work - yes, you add one period of GTM and...

    Nice work - yes, you add one period of GTM and JtotCC together.

    See AP32244 AURIX SYSPLL Frequency Modulation for a very long discussion of PLL modulation effects on short and long term jitter.
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    See...

    See TriCore_TC162P_core_architecture_vol_1_of_2.pdf, Chapter 10 for details:
    - There are 18 data ranges (DPRx) and 10 code ranges (CPRx)
    - The six sets of protection set registers (CPXE, DPRE,...
  19. See the State Machine diagram in the TLF35584...

    See the State Machine diagram in the TLF35584 datasheet - when the TLF is in STANDBY state, LDO_uC is OFF, while LDO_Stby is SELECTED. While still in WAKE state, you can disable LDO_Stby (QST) by...
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    At the end of the day, Infineon just makes the...

    At the end of the day, Infineon just makes the AURIX - those details are up to your application :)

    For further guidance, see ISO 26262-6:2018 and ISO 26262-9:2018. Separating software elements by...
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    The CPU Memory Protection Unit is used to enforce...

    The CPU Memory Protection Unit is used to enforce freedom from interference between software components.

    I find it helpful to think of a secure building, where each employee (task) is given one of...
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    Just to be sure - can you dump a bit of memory at...

    Just to be sure - can you dump a bit of memory at 0x8001C000?

    Could it be that there's an interrupt handler that isn't saving and restoring D15 in between those instructions?
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    In the iLLD demos package, there's a folder...

    In the iLLD demos package, there's a folder called "EvadcBasicDemo". I don't see anything in Github for the TC3xx EVADC yet.
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    There are lots of examples in the AURIX...

    There are lots of examples in the AURIX Development Studio:
    https://www.infineon.com/cms/en/product/promopages/aurix-development-studio/

    Note that most examples are for the TC377, but the TC375...
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    There's a Lcf_Dcc_TriCore_Tc.lsl that comes with...

    There's a Lcf_Dcc_TriCore_Tc.lsl that comes with the Base Framework package for the TC38A - see attached.

    To sign up for a MyICP account, and scroll down to the bit that says "Access to complete...
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