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Type: Posts; User: cwunder

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  1. Replies
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    This means it is using the interrupt vector table...

    This means it is using the interrupt vector table for CPU0. On TC399 you can have 6 CPUs meaning you can have 6 interrupt vector tables.
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    In the user's manual you can review the User...

    In the user's manual you can review the User Configuration Block options.



    For PFlash protection this is controlled by the UCB_PFlash. Within this UCB you have the option to protect the PFlash...
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    Do you mean HighTec EDV-Systeme GmbH? You open...

    Do you mean HighTec EDV-Systeme GmbH?

    You open an example project that uses interrupts.

    Basically you need to install the interrupt and then enable it. Here is a snippet that I did in the past...
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    Sorry that you had troubles: I did what to point...

    Sorry that you had troubles: I did what to point out that the user's manual does describe how the parity is being generated and used. From the users perspective you don't need to worry about it as it...
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    To create an interrupt entry it usually involves...

    To create an interrupt entry it usually involves two parts. You have to have a table defined in your linker/locator file and then you need to create the entry with a keyword or macro in a source file...
  6. Thread: Tc275 - gtm -

    by cwunder
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    Have you looked at section "25.22.2.1 Port to GTM...

    Have you looked at section "25.22.2.1 Port to GTM Control Registers"? Then for what is available at the TIMx look at Table 25-7x.
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    Each interrupt source is assigned a unique...

    Each interrupt source is assigned a unique interrupt priority number known as the Service Request Priority Number (SRPN). On receipt of an interrupt request from an interrupt source the SRPN is used...
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    The vector table is defined in the linker/locator...

    The vector table is defined in the linker/locator file. You add the interrupt function in your source code such that the linker can add the location of your ISR in the table. The TOS indicates which...
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    The interrupts all basically work the same and...

    The interrupts all basically work the same and follow the common definition of the Service Request Control Register (SRC). You need to choose the SRPN that matches the entry in the vector table. This...
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    Enclosed is the formula from the user's manual...

    Enclosed is the formula from the user's manual (TQ=0, Q=24, A=3,B=1 and C=3, fPER=200MHz):
    3948
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    Sorry but I have to comment that you are asking a...

    Sorry but I have to comment that you are asking a question without really giving enough information.

    Is this the crystal frequency? As usually the peripheral PLL is used (fPLL2) and typically...
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    When writing to the special function registers...

    When writing to the special function registers you need to check the access rights. The PDISC register has the following access rights SV, E, P. Which means you must be in supervisor mode, is CPU...
  13. It is hard to judge the difficulty you are...

    It is hard to judge the difficulty you are experiencing as everyone has a different background without knowing your issues? With TC297 this is the highest end device for the family however most...
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    Download the free trial of the Hightec or Tasking...

    Download the free trial of the Hightec or Tasking tool chains.
    Then sign up for an myICP account and then you can download the software frameworks and demos.
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    You could use 8-bit transfer and perform three of...

    You could use 8-bit transfer and perform three of them. If you keep the transmit buffer full it will look like one continuous transfer which means you can use the automatic chip select.
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    I am assuming your drawings are displaying the...

    I am assuming your drawings are displaying the LSB (parity) as the left most bit.

    The BACON.PARTYP = 0 defines EVEN parity. Your expected data is showing ODD parity (5 Ones).

    The AURIX is...
  17. The ECC on the PFlash is calculated over 256 data...

    The ECC on the PFlash is calculated over 256 data bits and the address bits. The data is stored in Flash with error correcting codes “ECC” in order to protect against data corruption.

    You should...
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    The SPI CLC register is CPU ENDINIT protected....

    The SPI CLC register is CPU ENDINIT protected. You have used the "Safety ENDINIT" function.

    You can check the register access via the function register table in the chapters.
    3741
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    The zip file contains many more zip file in which...

    The zip file contains many more zip file in which one is called iLLD_1_0_1_8_0_TC2xx_Demos.zip.

    3740
  20. The MCAL drivers are not free. You need to...

    The MCAL drivers are not free. You need to contact your Infineon representative for pricing as it depends on what packages you want. They can also provide a link to download them.
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    Your request seems impractical as the STM is not...

    Your request seems impractical as the STM is not directly connected to a port pin.
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    If you are using a kernel (RTOS) then most likely...

    If you are using a kernel (RTOS) then most likely the system timer is used as the scheduler (based on the kernel tick time, for example 1 msec).

    The system timer discussion in this thread is...
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    Have you asked Tasking directly? In the past they...

    Have you asked Tasking directly? In the past they supported Windows, Linux and Solaris.
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    Generally for the STM to provide a period event....

    Generally for the STM to provide a period event. You need to read the current STM timer value (CMP0) and add the compare value to it then write the result back to the compare register. This will set...
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    The clock for the STM is derived from the SPB. If...

    The clock for the STM is derived from the SPB. If you have 200MHz system frequency I would expect the SPB frequency to be 100MHz.

    Two parameters are programmable for the compare operation:
    1....
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