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Type: Posts; User: UC_wrangler

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    Here is a little example of overlay. I wrote it...

    Here is a little example of overlay. I wrote it for a TC27x, so it's using OVC2 (CPU2 overlay registers) instead of OVC0, and it remaps PFLASH access to LMU RAM, so you'll need to adapt the...
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    Possibly important to note that using DMA isn't...

    Possibly important to note that using DMA isn't really faster, because there's a bit of overhead in arbitrating between DMA channels and swapping transaction sets in and out. A good general...
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    The GTM is pretty slow on the SPB. Is...

    The GTM is pretty slow on the SPB. Is PeriodArray in local DSPR? That will only help a tiny bit.

    You could make a gigantic DMA linked list to do the transfers from PeriodArray into...
  4. Yes - if you're using circular buffering, the...

    Yes - if you're using circular buffering, the buffer should be aligned. E.g., align a 1K circular buffer on a 1K boundary.
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    Yes, it's possible for the HSM to control the MTU.

    Yes, it's possible for the HSM to control the MTU.
  6. Usually, the TC2xx FlexRay PLL or TC3xx...

    Usually, the TC2xx FlexRay PLL or TC3xx Peripheral PLL is close enough for 1 Mbps and slower, but not for CAN FD. Each OEMs has strict requirements that dictate the CAN clock source, and sometimes...
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    If you mean that you only want CPU3 to be able to...

    If you mean that you only want CPU3 to be able to access CAN1 and LIN1, then you'll want to use the access enable registers for those peripherals, to restrict which bus masters have access.

    For...
  8. ECC errors in DFLASH do not cause a bus error. ...

    ECC errors in DFLASH do not cause a bus error. Instead, read errors are reported via HF_ECCS (for DF0) and SF_ECCS (for DF1).

    What is causing the reset? Is there an SMU alarm? Is there a CPU...
  9. STM, PSI5, PSI5S, HSSL, HSCT: 1 additional wait...

    STM, PSI5, PSI5S, HSSL, HSCT: 1 additional wait state
    DMA, ERAY, I2C: 2
    GETH - 4
    EVADC-8
    EDSADC -8
    CONVCTRL-8
    MTU(SSH) - 9
    GTM - 9
    PMS - 8
    Peripherals not listed above: 1 SPB wait state
  10. Check out Table 3-37 PLL Peripheral in the...

    Check out Table 3-37 PLL Peripheral in the datasheet.

    "Peak accumulated jitter" is +/- 700 ps. The accumulated jitter over a single bit time interval (e.g., 500 ns @ 2 Mbps) is a little less than...
  11. You've already made this request elsewhere. ...

    You've already made this request elsewhere. Please help us answer questions more efficiently by letting one person focus their efforts.
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    uCLinux is your only hope, but it's mostly...

    uCLinux is your only hope, but it's mostly abandoned. It generally requires much more RAM than is available on an AURIX.
  13. There isn't enough RAM for uCLinux.

    There isn't enough RAM for uCLinux.
  14. But isn't A5=8000E4B7 before the trap? That...

    But isn't A5=8000E4B7 before the trap? That looks outside of your ranges. Odd that DEADD is something else though.
  15. Ah, but since the devices are in production now,...

    Ah, but since the devices are in production now, the flood gates have been opened:

    User Manual Part 1...
  16. Sorry, my previous post wasn't correct - there's...

    Sorry, my previous post wasn't correct - there's just one QCTRL register per queued source, not one for each channel.

    Converting multiple instances of the same channel is usually handled by having...
  17. View Post

    <removed woefully incorrect suggestions>
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    Did you enable the ASCLIN peripheral first with...

    Did you enable the ASCLIN peripheral first with something like this?


    // enable the peripheral
    IfxScuWdt_clearGlobalEndinit( IfxScuWdt_getGlobalEndinitPassword() );
    ...
  19. I wouldn't worry about Tuning Protection. That...

    I wouldn't worry about Tuning Protection. That documentation is hard to get.

    Otherwise, you're on the right track. If you decide to add HSM software later, reserving perhaps the first 256K is a...
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    If you want to change an output back to GPIO, you...

    If you want to change an output back to GPIO, you can set its IOCR register from an alternate output function (>=1) back to GPIO (0).

    For example, for pin 65 / P15.5:

    P15_IOCR4.B.PC5 = 0x11; ...
  21. It's not only possible, it's mandatory: each core...

    It's not only possible, it's mandatory: each core has its own set of Memory Protection and Safety Memory Protection registers.

    The Memory Protection Unit limits what ranges that particular CPU is...
  22. No, it's not - but it could be that your linker...

    No, it's not - but it could be that your linker file is not handling the PSPR copy correctly.

    Here's a ilttle example that does both CPU Memory Protection and Safety Memory Protection.

    ...
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    Well... TC37x instead of TC27x, but you could...

    Well... TC37x instead of TC27x, but you could just modify the TC39x scripts, and cut memory from 16 MB to 6 MB.
  24. __private is generally used to put a function...

    __private<n> is generally used to put a function in one core's PSPR (Program Scratch Pad) memory. It doesn't prevent another core from calling the function - but if another core does, it will likely...
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    When a debugger is connected, the watchdog system...

    When a debugger is connected, the watchdog system is disabled by default. Could it be that that line just happens to be where the watchdog expires? Which alarm are you seeing?
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