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Hi, I'm using CYT4BF.

I confirmed that the Bandgap Reference circuits can be set to higher current mode or low power in the PWR_CTL2.BGREF_LPMODE register.

1) Can you explain in more detail the higher current mode and low power mode of Bandgap Reference circuits?
2) Can you tell me in what cases the PWR_CTL2.BGREF_LPMODE register is used?

BR.

taegyunahn.

Hi!

I've grown an inherited mess into a now now-useful application running on PSOC 5LP (CY8C5868AXU-035), using PSOC Creator 4.4.

We burn our board FW using  KitProg 'dongles' connected to the SWD port + PSocProgrammer v3.29.5 - so far so good.

But we will need to make this a UART bootloaded app, with UART bootloader, for the 'real world'. 
 
    [info: currently..  C code: ~49K flash/13K RAM; 
                                        296K .cyfit file / 7.5K  config.hex
                                        650K project hex file;
                                        future: RAM use will decrease a bit, C flash code will grow maybe 5-10 K]

1.   I have documents on bootload and broad understanding,  but where is link to ZIP file sources? 
       Found some old dead Cypress links, or links to irrelevant PSOC4 or 6 platforms...  
       Do please direct me to current valid PSOC5  code working on PSOC Creator 4.4  so I can begin to
       play with it without pulling my hair using wrong/stale stuff, errors etc.

2.   Where is the downloadable PC host app?   Ideally I would like some command line C code to
       download/burn .HEX file - small possibility exists this code might be wrangled onto an Android
       platform some future time.   

3.  Approx expected time from FW burn thru reset into acutal app (not counting 2 sec delay) for a
      650K Hex project file @ 115Kbps-8N1 serial rate? 


At first glance it seems easiest to me to use exactly the same "soft hardware" from our FW app to build the
bootloader  (which has fixed 115Kbps UART used for logging/configuration etc.)   so that there is no "discontinuity" between the entities  (other than "bootload" vs "bootloadable" distinction).

Any other guidance/tips welcome. 


Thanks,
Bill

Hello, 

As a result of the difficulties of ModusToolbox i have been attempting to use the Mbed Studio with the PSoC64 Wi-Fi BT Secure Boot Pioneer kit. I have been able to build the given program 'mbed-os-example-blinky' as well as debug it. However it is not not working as anticipated. I believe the LED is not mapped to the correct GPIO pin on the board. Does anyone know how to do this?

Hello everyone, I use MCU that has 3V3 output and 5V input tolerant pins, but for my application I need to have 5V output and 5V tolerant input pins. How can I achieve this? Expander is not in the option because it needs SPI/I2C drivers in firmware, and I want to avoid that. I can make 3V3 pin output into 5V pin output using MOSFETs but then the input part is tricky. 
Thanks in advance ! 

Dear team

I would like to use the MA5302 to create a single-supply, single-ended input stereo amplifier.

There was an evaluation board for MA5302 with positive and negative power supplies and single-ended input, but this does not seem to be compatible with a single power supply.

Therefore, I am thinking of creating a circuit for 2 channels using the evaluation board below as a reference.

https://www.infineon.com/cms/jp/product/evaluation-boards/ref_ma5332btlsps/

I have two questions regarding the above.

① Does the supply voltage need to be +40V?

Since I only need to be able to get an output of about a few tens of W, I would like to first make a simple evaluation using a commercially available switching power supply.

(If possible, we would like to be able to evaluate by inputting 30V or less.)

② If I use a single power supply, do I need to make the audio input differential?

I would like to use single-ended input if possible.

Best Regards,

TOMMAT

Hi,

Can you please advise if the CYW20829B0-P4 module supports Zephyr? If not, is there any plan for that?

Regards,

Marcelo Macedo - FAE at Neutronics

Hello,

we ported the wifi stack in our new product, it has a WiFi stability issue, mainly it shows SDIO bus communication error, we made a restart stack when it happened but we don't know where is the root cause, can you help us with this?

Thank you very much!

•  setup
  • pack: https://github.com/Infineon/AIROC-Wi-Fi-Bluetooth-STM32
  • module/chipset: COMPONENT_4373/COMPONENT_MURATA-2AE
  • after connecting to AP, send a request to fetch RSSI every 5 seconds
  • WHD/WCM logging enabled
  • host MCU:STM32H7B3LI, interface by SDIO
  • RTOS: ThreadX
• issue
  • got an error on "SDIO bus failed to come up , whd_kso_enable failed" from time to time, sometimes shows up just after connecting to AP, and sometimes happens a few minutes after
  • few changes from the stack but no improvement:
    • force speed as 25MHz ( not jump to 50MHz)
    • force to use memory copy to internal RAM for DMA () --  bool "use_temp_dma_buffer = true"
    • #define CYBSP_WIFI_SDIO_NEEDS_INIT (0)
    • some timing/retry change to long
      • #define SDIO_ENUMERATION_TRIES (1000)
        #define SDIO_RETRY_DELAY_MS (2)
        #define SDIO_BUS_LEVEL_MAX_RETRIES (200)
      • #define SPINWAIT_POLL_PERIOD 20
      • #define KSO_WAIT_MS (2)
        #define MAX_KSO_ATTEMPTS (1000)

We have been working on debugging an issue where the TC29x Ethernet receiver halts after being saturated with messages and the Ethernet module must be restarted for the receiver to continue receiving messages. We have seen this behavior on two of our designs and on the TC2X9 Triboard. In debug mode the Receive Watchdog Timeout bit causes an interrupt and data corruption is seen when reviewing the Rx buffers. This eventually leads to the receiver halting, no longer receiving any messages and the missed FIFO counter being filled with the missed messages. We are trying to determine the root cause of the data corruption and the halting of the receiver. Any help on this would be greatly appreciated.

Note, with our current test configuration we have also seen that disabling the "Automatic Pad or CRC Stripping" and "CRC Stripping of Type FRAMES" in the MAC configuration prevents the receiver from halting, but we would like to know the root cause of this issue.

Hi Everyone,

Today we are manufacturing sensors using the assembly KMI15/1 manufactured by NXP. We need an alternative because KMI15/1 is obsolete. We are looking at the Infineon #TLE4941PLUSC. The data sheet mentions that it needs a magnet on the back side - that solution is very similar to the KMI15/1. This is a link to the NXP assembly KMI15/1

KMI15/1 Integrated rotational speed sensor (nxp.com)

Can you provide the sensor TLE4941PLUSC (or similar) with that magnet attached to it?

Thank you, it would be great to see your answer. 

I can program the psoc5 using openocd now, with some caveats. However, if an NVL entry exists, it stops.

I have a project which somehow did something to the NVL.

I understand setting the Reset condition on the Pins can cause this.  However, setting the pins to Don't Care doesn't fix this problem, so I suspect something else is causing the NVL to change.

Is there *any* gui / command line interface to find out what is causing the NVL to be set? (so it can be "fixed" in the project?)

This would not normally be a problem, but using openocd to program the psoc halts when the NVL entry is in the Creator generated hex file.  I have multiple reasons for using openocd, some of which involve production machines. Others are very fast compile/debug cycle.  (https://socmaker.com/?p=1004, and https://socmaker.com/?p=1027)

If I use objcopy, could I exclude that from the elf file for the new obj?  (before making a hex file) If so, would it be by address? If so, which address?  otherwise, how would I do that exclusion?

Is there a way to use openocd to program the NVL (perhaps kitprog in kitprog mode?) (Just checking)

Thanks!