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Hi support,

I would like to set-up a UART connection on my NAC1080 using the GPIO0 and GPIO2 in order to communicate with my PC the messages that the NAC1080 will be sending.

I've been reviewing the uart_drv.h library you have available and what I can't see is how the data transmission works.

There's a function called "transmit_bytes()" that send the Tx buffer data, but where's the Tx buffer? 

How could I edit the data on that buffer to be able to send the desired message?

Regards,

-K

The current TC397_TFT v1.0 development board uses the TC397 A step of the chip, but I see ADS are TC397 B step routines, I will ADS in a few examples compiled and burned to the development version, can not run normally, respectively, through the TASKING and winIDE DEBUG found that the chip startup process will enter the Context Maneger Error Trap, the following figure belongs to, please ask! Please ask:

1. For Context Maneger Error Trap should be solved in what way?

1. Current ADS 1.9.20 supports TC397 A step chip, if not support and TC397A step corresponding to the example tutorial?

2. What is the difference between TC397 A step and TC397 B step?

TASKING DEBUG

winIDE

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC397-TFT-v1-0%E5%BC%80%E5%8F%91%E6%9D%BF%E7%BC%96%E8%AF%91%E7%83%A7%E5%BD%95%E4%BB%BB%E6%84%8FADS%E7%A8%8B%E5%BA%8F%E4%BC%9A%E8%BF%9BContext-Maneger-Error-Trap/td-p/743094

Hello, everybody:

I encountered the following problem, read the value in the register, check the register is "0x80000e23", but after reading, the first bit is not read, only read "0xe23", the type of the variable used to receive the value of the register is ( volatile uint32 )

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/%E8%AF%BB%E5%8F%96%E5%AF%84%E5%AD%98%E6%9C%BA%E7%9A%84%E5%80%BC-%E7%AC%AC%E4%B8%80%E4%B8%AAbit%E8%AF%BB%E5%8F%96%E4%B8%8D%E5%88%B0/td-p/743090

I tried to configure it using the above code, but it reports an error at device.set_acquisition_sequence(sequence).

Using the sample program found in the official distance_fft.py, using the

Perform the configuration. Is there any way to use config to configure it, or convert config to metrics and then configure it?

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E9%9B%B7%E8%BE%BE%E4%BC%A0%E6%84%9F%E5%99%A8/BGT60TR13C-%E5%A6%82%E4%BD%95%E4%BD%BF%E7%94%A8%E5%8F%82%E6%95%B0%E9%85%8D%E7%BD%AE%E4%BC%A0%E6%84%9F%E5%99%A8%E8%8E%B7%E5%8F%96%E6%95%B0%E6%8D%AE/td-p/743081

大家好！

官方程序里的延时函数Delay_us(uint32 delay_time_us)，在实际测试时，有个奇怪的现象。

测试程序看门狗设置1008ms，测试程序延时方式如下：

1. Delay_us(500000); (void)WDT1_Service();     //延时500ms，喂狗
2. Delay_us(600000); (void)WDT1_Service();     //延时600ms，喂狗
3. Delay_us(1000000); (void)WDT1_Service(); //延时1000ms，喂狗

其中，1，3能正常工作，第2项延时600ms喂狗，程序没有喂狗成功，程序不工作。

This Q&A just discussed P/D Flash, AURIX™ MCU: Error Correction Code (ECC) support - KBA238244

My question: is there special ECC for  RAM and CAN relevant memory, e.g. Message RAM

Hello,

I am trying to flash littlefs filesystem on the qspi external serial flash memory in XMC7100 V1.1. As I see library mtb-littlefs is not included in the XMC7100 kit but i have included the mtb-littlefs from PSoc6 Kit to my project and in makefile included target as XMC7100 (my board).

BOARD: XMC7100 EVK Lite v1.1

Memory: External QSPI flash memory

These are the errors when I try to builld the file:

Initializing build: mtb-example-psoc6-filesystem-littlefs-freertos Debug APP_KIT_XMC71_EVK_LITE_V1 GCC_ARM

Prebuild operations complete

Auto-discovery in progress...
Auto-discovery complete
Commencing build operations...

Tools Directory: C:/Users/Prasad/ModusToolbox/tools_3.2
"Using linker bsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/COMPONENT_/TOOLCHAIN_GCC_ARM/linker.ld"

Constructing build rules...
Build rules construction complete

==============================================================================
= Building application =
==============================================================================
Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 223 file(s)
Compiling ../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c -DCOMPONENT_APP_KIT_XMC71_EVK_LITE_V1 -DCOMPONENT_CAT1 -DCOMPONENT_CAT1C -DCOMPONENT_CAT1C4M -DCOMPONENT_CM7 -DCOMPONENT_CM7_0 -DCOMPONENT_Debug -DCOMPONENT_FREERTOS -DCOMPONENT_GCC_ARM -DCOMPONENT_MW_ABSTRACTION_RTOS -DCOMPONENT_MW_CAT1CM0P -DCOMPONENT_MW_CLIB_SUPPORT -DCOMPONENT_MW_CMSIS -DCOMPONENT_MW_CORE_LIB -DCOMPONENT_MW_CORE_MAKE -DCOMPONENT_MW_FREERTOS -DCOMPONENT_MW_MTB_HAL_CAT1 -DCOMPONENT_MW_MTB_LITTLEFS -DCOMPONENT_MW_MTB_PDL_CAT1 -DCOMPONENT_MW_RECIPE_MAKE_CAT1C -DCOMPONENT_MW_RETARGET_IO -DCOMPONENT_RTOS_AWARE -DCOMPONENT_SOFTFP -DCOMPONENT_XMC7x_CM0P_SLEEP -DCORE_NAME_CM7_0=1 -DCY_APPNAME_mtb_example_psoc6_filesystem_littlefs_freertos -DCY_RETARGET_IO_CONVERT_LF_TO_CRLF -DCY_SUPPORTS_DEVICE_VALIDATION -DCY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V1 -DCY_USING_HAL -DDEBUG -DLFS_THREADSAFE -DTARGET_APP_KIT_XMC71_EVK_LITE_V1 -DXMC7100D_F176K4160  -I. -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1 -Ibsps -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config/GeneratedSource -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config -Ilibs/abstraction-rtos/include -Ilibs/abstraction-rtos -Ilibs/abstraction-rtos/include/COMPONENT_FREERTOS -Ilibs/cat1cm0p/COMPONENT_CAT1C -Ilibs/cat1cm0p -Ilibs/clib-support -Ilibs/clib-support/TOOLCHAIN_GCC_ARM -Ilibs/cmsis/Core/Include -Ilibs/cmsis/Core -Ilibs/cmsis -Ilibs/core-lib/include -Ilibs/core-lib -Ilibs/freertos/Source/include -Ilibs/freertos/Source -Ilibs/freertos -Ilibs/freertos/Source/portable/COMPONENT_CM7 -Ilibs/freertos/Source/portable -Ilibs/freertos/Source/portable/COMPONENT_CM7/TOOLCHAIN_GCC_ARM -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/pin_packages -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C -Ilibs/mtb-hal-cat1 -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers -Ilibs/mtb-hal-cat1/include -Ilibs/mtb-hal-cat1/include_pvt -Ilibs/mtb-hal-cat1/source -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C -Ilibs/mtb-pdl-cat1/devices -Ilibs/mtb-pdl-cat1 -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip -Ilibs/mtb-pdl-cat1/drivers/include -Ilibs/mtb-pdl-cat1/drivers -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet/include -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet -Ilibs/mtb-pdl-cat1/drivers/third_party -Ilibs/retarget-io -I../mtb_shared/mtb-littlefs/latest-v2.X/bd -I../mtb_shared/mtb-littlefs/latest-v2.X -I../mtb_shared/mtb-littlefs/latest-v2.X/include 
../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c:487:5: error: 'cy_stc_smif_mem_device_cfg_t' has no member named 'mergeTimeout'
  487 |     .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
      |     ^
make[1]: *** [libs/core-make/make/core/build.mk:283: C:/Users/Prasad/mtw/Littlefs_Filesystem/Littlefs_Filesystem/build/APP_KIT_XMC71_EVK_LITE_V1/Debug/ext/mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.o] Error 1
make: *** [libs/core-make/make/core/main.mk:385: secondstage_build] Error 2
"C:/Users/Prasad/ModusToolbox/tools_3.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/Prasad/ModusToolbox/tools_3.2 CY_IDE_BT_TOOLS_DIR= -j8 --output-sync all" terminated with exit code 2. Build might be incomplete.

When I comment the line:

#if (CY_IP_MXSMIF_VERSION >= 2)
    /** Continuous transfer merge timeout.
     * After this period the memory device is deselected. A later transfer, even from a
     * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
     * This configuration parameter is available for CAT1B devices. */
    //.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
#endif /* CY_IP_MXSMIF_VERSION */

I get failed to creat spi device block:

Could someone help me with ".mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE" error?

best regard,
PrasadA

Hi, I am new to radar sensors.

To analyze radar data, I have plotted FIFO data read from BGT60TR13C in time domain.

My concern is whether the data in the form below is read correctly.

Could you please tell me what the raw data in the time domain usually looks like and if it is correct?

Hello 

Can we allocate 2 nodes on MULTICAN_CONFIG_0, and operate all message objects of both the nodes using only one CAN_Rx and CAN_Tx through transceiver??