XMC™ Forum Discussions
Hello,
I open this issue to fix the problem previously explained here:
https://community.infineon.com/t5/XMC/XMC-usic-end-of-transmission/m-p/670732#M14418
as per requested, I attach the project I am using.
Best regards,
Lander
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Hello
Can we allocate 2 nodes on MULTICAN_CONFIG_0, and operate all message objects of both the nodes using only one CAN_Rx and CAN_Tx through transceiver??
Hello,
I am trying to use MULTICAN with XMC4700 Relax Kit, But i am unable to transmit data over it. I have attached my project below -
Please check my code and help me out with solution.
Dear All,
I use the DAVE ide v4 with the nano library, calling the SPI-MASTER-EnableSlaveSelectSignal() and SPI-MASTER-DisableSlaveSelectSignal() functions cannot raise or lower the CS pin of SPI. However, when sending data through SPI, when using an oscilloscope to check the status of SCL and MOSI pins, they generate waveforms that are normal, but the CS pin remains in a high level state.
Configure this CS pin as an IO port, manually pull up or down the CS pin, but use the BUSY flag in the TBUF register as the completion of sending. When pulling up the CS pin, there will be a situation where there is still one byte that has not been sent, but the CS pin has been pulled up.
What may be the reason why the two API functions generated by calling cannot control the CS pin state; How can I avoid manually raising or lowering the CS pin when there is still one byte of data not sent?
Thanks.
Show LessHello,
I am trying to flash littlefs filesystem on the qspi external serial flash memory in XMC7100 V1.1. As I see library mtb-littlefs is not included in the XMC7100 kit but i have included the mtb-littlefs from PSoc6 Kit to my project and in makefile included target as XMC7100 (my board).
BOARD: XMC7100 EVK Lite v1.1
Memory: External QSPI flash memory
These are the errors when I try to builld the file:
Initializing build: mtb-example-psoc6-filesystem-littlefs-freertos Debug APP_KIT_XMC71_EVK_LITE_V1 GCC_ARM
Prebuild operations complete
Auto-discovery in progress...
Auto-discovery complete
Commencing build operations...
Tools Directory: C:/Users/Prasad/ModusToolbox/tools_3.2
"Using linker bsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/COMPONENT_/TOOLCHAIN_GCC_ARM/linker.ld"
Constructing build rules...
Build rules construction complete
==============================================================================
= Building application =
==============================================================================
Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 223 file(s)
Compiling ../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c -DCOMPONENT_APP_KIT_XMC71_EVK_LITE_V1 -DCOMPONENT_CAT1 -DCOMPONENT_CAT1C -DCOMPONENT_CAT1C4M -DCOMPONENT_CM7 -DCOMPONENT_CM7_0 -DCOMPONENT_Debug -DCOMPONENT_FREERTOS -DCOMPONENT_GCC_ARM -DCOMPONENT_MW_ABSTRACTION_RTOS -DCOMPONENT_MW_CAT1CM0P -DCOMPONENT_MW_CLIB_SUPPORT -DCOMPONENT_MW_CMSIS -DCOMPONENT_MW_CORE_LIB -DCOMPONENT_MW_CORE_MAKE -DCOMPONENT_MW_FREERTOS -DCOMPONENT_MW_MTB_HAL_CAT1 -DCOMPONENT_MW_MTB_LITTLEFS -DCOMPONENT_MW_MTB_PDL_CAT1 -DCOMPONENT_MW_RECIPE_MAKE_CAT1C -DCOMPONENT_MW_RETARGET_IO -DCOMPONENT_RTOS_AWARE -DCOMPONENT_SOFTFP -DCOMPONENT_XMC7x_CM0P_SLEEP -DCORE_NAME_CM7_0=1 -DCY_APPNAME_mtb_example_psoc6_filesystem_littlefs_freertos -DCY_RETARGET_IO_CONVERT_LF_TO_CRLF -DCY_SUPPORTS_DEVICE_VALIDATION -DCY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V1 -DCY_USING_HAL -DDEBUG -DLFS_THREADSAFE -DTARGET_APP_KIT_XMC71_EVK_LITE_V1 -DXMC7100D_F176K4160 -I. -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1 -Ibsps -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config/GeneratedSource -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config -Ilibs/abstraction-rtos/include -Ilibs/abstraction-rtos -Ilibs/abstraction-rtos/include/COMPONENT_FREERTOS -Ilibs/cat1cm0p/COMPONENT_CAT1C -Ilibs/cat1cm0p -Ilibs/clib-support -Ilibs/clib-support/TOOLCHAIN_GCC_ARM -Ilibs/cmsis/Core/Include -Ilibs/cmsis/Core -Ilibs/cmsis -Ilibs/core-lib/include -Ilibs/core-lib -Ilibs/freertos/Source/include -Ilibs/freertos/Source -Ilibs/freertos -Ilibs/freertos/Source/portable/COMPONENT_CM7 -Ilibs/freertos/Source/portable -Ilibs/freertos/Source/portable/COMPONENT_CM7/TOOLCHAIN_GCC_ARM -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/pin_packages -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C -Ilibs/mtb-hal-cat1 -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers -Ilibs/mtb-hal-cat1/include -Ilibs/mtb-hal-cat1/include_pvt -Ilibs/mtb-hal-cat1/source -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C -Ilibs/mtb-pdl-cat1/devices -Ilibs/mtb-pdl-cat1 -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip -Ilibs/mtb-pdl-cat1/drivers/include -Ilibs/mtb-pdl-cat1/drivers -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet/include -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet -Ilibs/mtb-pdl-cat1/drivers/third_party -Ilibs/retarget-io -I../mtb_shared/mtb-littlefs/latest-v2.X/bd -I../mtb_shared/mtb-littlefs/latest-v2.X -I../mtb_shared/mtb-littlefs/latest-v2.X/include
../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c:487:5: error: 'cy_stc_smif_mem_device_cfg_t' has no member named 'mergeTimeout'
487 | .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
| ^
make[1]: *** [libs/core-make/make/core/build.mk:283: C:/Users/Prasad/mtw/Littlefs_Filesystem/Littlefs_Filesystem/build/APP_KIT_XMC71_EVK_LITE_V1/Debug/ext/mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.o] Error 1
make: *** [libs/core-make/make/core/main.mk:385: secondstage_build] Error 2
"C:/Users/Prasad/ModusToolbox/tools_3.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/Prasad/ModusToolbox/tools_3.2 CY_IDE_BT_TOOLS_DIR= -j8 --output-sync all" terminated with exit code 2. Build might be incomplete.
When I comment the line:
#if (CY_IP_MXSMIF_VERSION >= 2)
/** Continuous transfer merge timeout.
* After this period the memory device is deselected. A later transfer, even from a
* continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
* This configuration parameter is available for CAT1B devices. */
//.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
#endif /* CY_IP_MXSMIF_VERSION */
I get failed to creat spi device block:
Could someone help me with ".mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE" error?
best regard,
PrasadA
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I am design a new application where XMC4800 is used as EtherCAT slave with PMSM FOC.
I started with EtherCAT slave stack demo for XMC4800 and I added PMSM FOC app.
I successfully control the PMSM motor in openloop, just rotating the vector in current mode. The slave stack code runs wihtout problem with TwinCAT.
Unfortunately, when I tried to use the speed loop control with Motorlib calls, the XMC has probably problem with interrupt.
I have a general questions:
1) XMC4800 hardware is able to manage EtherCAT slave and PMSM FOC at the same time ?
2) There is some example with this configuration available ?
3) There are something to configure to avoid problem with Interrupt. I used analog input to capture SIN/COS encoder, motor current, dc bus currents, etc...
Let me know
Regards
Ing. Marco Gavesi
NilLAB GmbH
Show LessHello Infineon,
My project requires using the SMIF (Octal SPI) to transfer from external flash memory into XMC7200 internal RAM through P-DMA.
Based on the 1-D definition of P-DMA in the XMC7200, the maximum transfer size is dependent on the "X_COUNT",
Where "X_COUNT" have a maximum of 256 iterations,
Which equals a maximum of 256*1 Bytes = 256 B of data transferred every P-DMA transfer, assuming 8-bit data element each transfer.
1. Is there a maximum sequential P-DMA transfer constraint that we should be aware through this approach (SMIF (Octal SPI) to Internal RAM through P-DMA)?
2. If I have 16kB (64 sets of 256 B) of total data to be transferred through P-DMA, is there any easy way to automate and chain this 64 sets of transfer together without the microcontroller being involved after P-DMA transfer have started?
3. Or must the microcontroller be involved after each 256B of data transferred through every P-DMA transfer?
4. If so, is the overhead time spent between each P-DMA reprogramming and triggering significant or in the microsecond order of magnitude?
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Hi,
Looking at the latest ModusToolBox 3.2 I couldn't find an Ethercat Example for the board KIT_XMC48_RLX_ECAT_V2.1, is there any plan to port the Dave example to MTB as well?
Best Regards,
Marcelo Macedo - FAE at Neutronics
Show LessI am running bldc motor with the help of hall sensor but not able to get full no load speed.This motor has 1000 rpm but getting only upto 3500 rpm.
I am using example code to drive this motor whether this code support 10000 rmp.
My motor is working at 48v,750 W.Could you help to resolve this problem
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