AURIX™ Forum Discussions
#TC387
Hello, I meet with a problem when flash to B bank using bootloader. After having flashed, the B bank filled with 0xFF, if config A bank as active bank, the A bank filled with oxFF, do you know some possible reasons?
Show Lessi need some code to output Complementary PWM
Hi I need to fetch data from ethernet module in ethernet_input function. But it crashes if I try to fetch anything.
ethernet_input(struct pbuf *p, struct netif *netif)
Is there any way to get data from there? I need to make some CAN packet using those.
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1. We are aware about UCB DBG to lock debug interface using 256 bit Password and unlock it.
2. We would like to know if Aurix TC32LP has the mechanism to lock JTAG permanentely ? Here we may not need to unlock it once locked. May be some kind of bit in registers which triggers permanent locking of JTAG debug interface.
Currently, we are checking out if there is any possibility to permanently lock JTAG.
From user manual, I did understand that to do a JTAG lock with PSW protection we need to update PROCONDBG register, then, after reset, the new values will be applied from UCB_DBG_ORIGIN and UCB_DBG_COPY and JTAG will not be accessible anymore.
This registers, UCB_DBG_ORIGIN and UCB_DBG_COPY, are located at addresses 0xAF402400 and 0xAF403400 for TC32LP.
In PROCONDBG register we are disabling access to JTAG by setting DBGIFLCK to 1. By doing so JTAG will be disabled at next reset.
Currently, we are using UDS services to provide a password and to lock/unlock JTAG access. So, in this way if we accidentally lock it we’ll be able to unlock it.
What we’d like to know if it is possible to lock JTAG interface permanently without any way of unlocking it no matter what way. Is there this kind of possibility to do so?
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I want set the MCU to Sleep mode once the system need, but i find some doubt points during i implemented.
1. In order to ask the peripheral module accordingly enter into Sleep state , i need set the EDIS to 0 firstly, but i can not confirm when i should set back this bit to 1 ? it will be set back to 1 by hardware?
2, please check following figure , the cpu apart from master will remain in the idle state after wake up source log in . will i need set the CPU aparting from Master to run state by sw?
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Hi,
I can write 8 bytes of data in DFLASH memory using page address. I need to write a single byte of data at any memory address.
Is it possible to write a single byte of data at any memory address location?
Thanks
Show LessI configure the SPU to do 256-point range FFT with input data from RIF, and then compare FFT result between SPU and other FFT library (Python numpy.fft).
For some input data as in picture below, upper plot is time domain signal of small noise fluctuation, ADC value varies from 1750 to 2000. The lower plot is FFT result from SPU and numpy.fft, and they aligns with each other so well that we can only see one green line. (except for one point at bin 0).
This shows the whole setup and SPU configuration is somewhat correct.
However, for input data with larger fluctuation as in following picture (noise + 100kHz sine wave with ADC value varies from 1920 to 2120), the FFT difference between SPU (red line) and numpy.fft (green line) is huge. SPU result shows much higher noise floor.
Moreover, if I further increase the input amplitude as in following picture (ADC value varies from 1400 to 2600), surprisingly SPU results' noise floor reduced, but 100kHz frequency's amplitude also reduced, and some artifact frequency component showed up.
Here is my SPU configuration:
/* INPUT SOURCE */
cfg->input.dataSource = IfxSpu_DataSource_rif0;
cfg->input.rif.numAntennae = IfxSpu_Num_Antennae_2;
cfg->input.rif.dataFormat = IfxSpu_InputDataFormat_real;
cfg->input.rif.dataType = IfxSpu_InputDataType_unsigned;
cfg->input.rif.sampleCount = 256;
cfg->input.rif.numRamps = 256;
IfxSpu_setupInput(slot, &cfg->input);
/* BIN-REJECTION */
cfg->binrej.mode = IfxSpu_BinRejection_Mode_reject;
cfg->binrej.numAllowedBins = 128;
cfg->binrej.thresholdEnabled = FALSE;
cfg->binrej.thresholdValue = 0xFFFFu;
IfxSpu_setupBinRejection(slot, &cfg->binrej);
IfxSpu_PassId passId = IfxSpu_PassId_0;
IfxSpu_PassConfig *pcfg = &cfg->pass[passId];
/* MATH 1 */
pcfg->math1.loaderExponent = 5;
pcfg->math1.numDropFirstSamples = 0;
pcfg->math1.numDropLastSamples = 0;
pcfg->math1.numPadFrontSamples = 0;
pcfg->math1.window.enabled = FALSE;
pcfg->math1.window.dataFormat = IfxSpu_WindowDataFormat_real16;
pcfg->math1.window.baseAddress = IFX_OFFSETOF(SPU_Cmem0_Map_t, rWndw);
for (antNr = 0; antNr < RADAR_NUM_RX; antNr++)
{
pcfg->math1.window.antennaOffsets[antNr] = 0;
}
pcfg->math1.phaseShift = IfxSpu_PhaseShift_0;
IfxSpu_setupMath1(slot, passId, &pcfg->math1);
/* FFT ENGINE UNLOADER */
pcfg->fft.enabled = TRUE;
pcfg->fft.inversed = FALSE;
pcfg->fft.size = IfxSpu_getSizeCode(RADAR_FFT1_LEN);
pcfg->fft.dataFormat = IfxSpu_FftDataFormat_complex32Bit;
pcfg->fft.exponent = 0;
pcfg->fft.forceToReal = FALSE;
IfxSpu_setupFft(slot, passId, &pcfg->fft);
/* FFT OUTPUT */
pcfg->fftOut.enabled = TRUE;
pcfg->fftOut.baseAddress = IFX_OFFSETOF(SPU_Emem_Map_t, fft_range);
pcfg->fftOut.format = IfxSpu_ODP_Format_complexHalfFloat;
pcfg->fftOut.exponent = 16;
pcfg->fftOut.inPlace = FALSE;
IfxSpu_setupFftOutput(slot, passId, &pcfg->fftOut);
I tried changing math1.loaderExponent from 0 to 18, it only changes the scale of FFT result, and do not solve the problem.
I also tried changing fftOut.exponent, but it does not have any effect.
Please help.
Thank you very much.
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