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Forum: Aurix Forum

  1. Sticky Thread Sticky: AURIX™ Forum competition

    Looking for a way to help others and be rewarded for it? By simply sharing your knowledge at our AURIX™ Forum, you can win a special prize! ...

    Started by Huixian‎, Apr 6th, 2020 06:16 AM
    • Replies: 0
    • Views: 1,036
    Apr 6th, 2020, 06:16 AM Go to last post
  2. Sticky Thread Sticky: Quick Training for AURIX™

    Here you can find a Quick Training for AURIX™ (entry-level): ...

    Started by triki‎, Aug 6th, 2019 07:35 AM
    • Replies: 1
    • Views: 4,977
    Mar 19th, 2020, 05:25 PM Go to last post
  1. Erased Flash ECC ( When read by HSM Core), TC399

    I have query regarding 'Reading Erased PFlash by HSM Core' in Aurix TC399 Microcontroller. One of the use case in our product requires that HSM Core...

    Started by umair‎, May 23rd, 2020 02:26 AM
    ecc, exception, hsm, tc399
    • Replies: 1
    • Views: 72
    May 23rd, 2020, 08:22 AM Go to last post
  2. What is the source of SMU ALM8[16] in Aurix 2G?

    Hello Support, What is the source of SMU ALM8 in Aurix 2G? Is it only WDTSSR.TO bit or ALM8 can be due to any other event also? If not, then do we...

    Started by baexps_pr1‎, May 23rd, 2020 02:01 AM
    • Replies: 0
    • Views: 52
    May 23rd, 2020, 02:01 AM Go to last post
  3. TSIM Multiple ELF support / Peripheral simulation

    Hello, I have two questions regarding TSIM : 1. Does TSIM support loading of multiple ELF files ? 2. Where can we find the documentation for...

    Started by Oren‎, May 23rd, 2020 01:08 AM
    • Replies: 0
    • Views: 61
    May 23rd, 2020, 01:08 AM Go to last post
  4. Contentions between CPU vs SRI accesses to PSPR / DSPR

    Hi, After skimming carefully through the datasheet, application notes, and, more generally, the Web... I haven't been able to find any information...

    Started by eric_jenn‎, May 20th, 2020 12:54 AM
    • Replies: 4
    • Views: 149
    May 22nd, 2020, 10:31 AM Go to last post
  5. Is there any other way to execute cyclic interrupts in all three cores? GPT12

    Hi friends, My project need a function like this: an interrupt would be triggered every T seconds. And I need to apply it in all of three...

    Started by valerie‎, May 20th, 2020 05:16 AM
    gpt12, tc277
    • Replies: 2
    • Views: 91
    May 22nd, 2020, 09:17 AM Go to last post
  6. Debug and CPU registers error using DAP IF

    Dear All, I try to FLASHing TC397XE chip using the DAP IF. With DAP telegrams , I can halt main CPU (using the HARR issue). I saw, that corresponds...

    Started by alexeyPhyton‎, May 21st, 2020 08:50 AM
    • Replies: 6
    • Views: 92
    May 22nd, 2020, 07:40 AM Go to last post
  7. Aurix 2G SMU Software Monitor Alarms across multiple CPU Cores and Safety WDT

    Hello Support, In Aurix 2G, there is Software Monitor Alarm possible. There are multiple Software Monitor Alarms which are assigned to different...

    Started by baexps_pr1‎, May 21st, 2020 03:13 PM
    • Replies: 7
    • Views: 76
    May 22nd, 2020, 07:16 AM Go to last post
  8. What is fail action for Core CPU WDT Write from alternate CPU?

    Hello Support, There are 3 Core CPU WDT within Aurix2G. So, Core 0 can write to Core CPU WDT0. Core 1 can write to Core CPU WDT1. ...

    Started by baexps_pr1‎, May 21st, 2020 06:04 PM
    • Replies: 3
    • Views: 57
    May 22nd, 2020, 05:17 AM Go to last post
  9. Is there PLL Range Check possible for Aurix 2G similar to Aurix 1G

    Hello Support, In Aurix 1G, there was PLL output range monitoring as shown below. Is there any way one can implement fPLL0 range monitoring in...

    Started by baexps_pr1‎, May 21st, 2020 08:42 AM
    • Replies: 5
    • Views: 85
    May 21st, 2020, 11:53 AM Go to last post
  10. Autosar for aurix

    Hi, I am working on Autosar, can anyone help me to know which tools to be use to generated code for different layers of Autosar.

    Started by KDN‎, May 21st, 2020 05:53 AM
    • Replies: 3
    • Views: 83
    May 21st, 2020, 11:32 AM Go to last post
  11. Does ACCEN Protection applicable for Core WDT in Aurix 2G?

    Hello Support, In the SCU Register set, there is ACCEN00 Register. Does Core CPU WDT access control possible using ACCEN register settings in Aurix...

    Started by baexps_pr1‎, May 21st, 2020 09:36 AM
    • Replies: 1
    • Views: 54
    May 21st, 2020, 10:01 AM Go to last post
  12. AURIX TC387 issues in Port and Mcu Modules in Tersos

    Attached images you can see error: (35016) is appearing consistently : Invalid XPath-expression for Attribute "MIN" of node "PortContainer":...

    Started by yehiahesham‎, May 19th, 2020 07:07 AM
    • Replies: 1
    • Views: 101
    May 21st, 2020, 06:55 AM Go to last post
  13. TC399 sector erase and write times

    Hi, I would like to understand the erase time and write time of a pfls sector. Where can this data be found?

    Started by kfir‎, May 21st, 2020 06:06 AM
    • Replies: 2
    • Views: 54
    May 21st, 2020, 06:20 AM Go to last post
  14. Functional difference between CCUCON3.4 and CCUCON4.24 bits Backuup Clock Monitor

    Hello Support, CCUCON3 Bit 4 as well as CCUCON4 Bit24, both says Back-Up Clock Monitoring Enable for Aurix 2G. There is only one set of Threshold...

    Started by baexps_pr1‎, May 20th, 2020 02:59 PM
    • Replies: 1
    • Views: 62
    May 21st, 2020, 06:20 AM Go to last post
  15. What is the source for TRAP2 bit in TRAPSTAT register in AURIX 2G?

    Hello Support, Shown below is a snippet from TRAPSTAT register Bit 2 . Can you please tell me what is the source for this TRAP2? What...

    Started by baexps_pr1‎, May 19th, 2020 11:32 AM
    • Replies: 3
    • Views: 137
    May 21st, 2020, 01:20 AM Go to last post
  16. new to Aurix, DMA not working

    Hi, I copied this right out of the manual. It should move 1 byte from source ('I') to overwrite the 'n' in the destination. It doesn't. I am in...

    Started by CharlieK‎, May 18th, 2020 02:14 PM
    • Replies: 3
    • Views: 520
    May 20th, 2020, 06:34 AM Go to last post
  17. Bus MPU settings and SSW execution after SWRSTCON.Bit1 Software Reset

    Hello Support, After the user configures the Bus MPU related registers according to the user program requirements, there is no Bus MPU SMU Alarm...

    Started by baexps_pr1‎, May 19th, 2020 05:34 PM
    • Replies: 0
    • Views: 64
    May 19th, 2020, 05:34 PM Go to last post
  18. RSTSTAT SMU Bit and TRAPSTAT SMUT Bit difference in Aurix 2G

    Hello Support, Can you please tell me under what condition RSTSTAT.SMU Bit 3 will be SET? Can you please tell me under what condition...

    Started by baexps_pr1‎, May 19th, 2020 12:37 PM
    • Replies: 0
    • Views: 62
    May 19th, 2020, 12:37 PM Go to last post
  19. Automatic reset cause

    Hi, I'm debugging the TC399B, and get a reset that's given from the SMU and FSP. (PSA) BUT, I cannot catch the point in the SW it occurs, I...

    Started by kfir‎, May 16th, 2020 10:57 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 292
    May 18th, 2020, 10:49 AM Go to last post
  20. Which HW Modules in AURIX™ are capable to generate PWM?

    Hi all, Does anyone know which HW Modules in AURIX™ are capable to generate PWM? #8042000 19454 Kind regards Bernie

    Started by Bernie‎, Dec 18th, 2019 04:02 AM
    • Replies: 6
    • Views: 1,362
    May 17th, 2020, 05:45 AM Go to last post

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