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Forum: Aurix Forum

  1. Sticky Thread Sticky: AURIX™ Forum competition

    Looking for a way to help others and be rewarded for it? By simply sharing your knowledge at our AURIX™ Forum, you can win a special prize! ...

    Started by Huixian‎, Apr 6th, 2020 06:16 AM
    • Replies: 0
    • Views: 1,086
    Apr 6th, 2020, 06:16 AM Go to last post
  2. Sticky Thread Sticky: Quick Training for AURIX™

    Here you can find a Quick Training for AURIX™ (entry-level): ...

    Started by triki‎, Aug 6th, 2019 07:35 AM
    • Replies: 1
    • Views: 5,046
    Mar 19th, 2020, 05:25 PM Go to last post
  1. issue SPI iLLD _interrupt trap

    Hello forum, we experience a strange issue with TC222 evalboard, while working with the iLLD. As base project template we are using the official...

    Started by pkqd‎, Today 12:34 AM
    illd, spi, tc222
    • Replies: 1
    • Views: 2
    Today, 12:39 AM Go to last post
  2. Aurix 2G SMU ALM8[10] configured as RESET will reset which cores?

    Hello Support, In Aurix 2G, SMU ALM8 is for Core 0 WDT Timeout Alarm. When this ALM8 is configured as RESET within the SMU using SMU_RESET ...

    Started by baexps_pr1‎, Yesterday 10:12 AM
    • Replies: 1
    • Views: 29
    Today, 12:06 AM Go to last post
  3. MTU module sample code get stuck at ( *mtuMemtest |= mask;)

    Hi everyone, I have the sample code MTU_MBIST for MTU module testing, which I download from github/aurix_code_example. However, everytime I run...

    Started by valerie‎, Yesterday 03:58 AM
    aurix tc277, mtu
    • Replies: 2
    • Views: 56
    Yesterday, 05:58 AM Go to last post
  4. can't download aurix-studio

    ive tried to download AURIX™ Development Studio software via the link given from aurix official website. but it kept to stop downloading from...

    Started by lsh9640‎, Mar 9th, 2020 05:27 PM
    • Replies: 5
    • Views: 685
    Yesterday, 05:54 AM Go to last post
  5. AURIX™ Development Studio installation error

    I downloaded the program through the site below. Integrated Development Environment ( IDE ) : AURIX™ Development Studio installation site :...

    Started by swyoon‎, Dec 25th, 2019 06:50 PM
    • Replies: 4
    • Views: 1,127
    May 27th, 2020, 04:06 PM Go to last post
  6. SENT sensor simulation

    Hi, I am working on a project, where a SENT sensor should be simulated. For that, the TC277 should behave as the Sensor and send a SENT signal to...

    Started by chrisB‎, May 26th, 2020 05:26 AM
    • Replies: 3
    • Views: 102
    May 27th, 2020, 01:45 PM Go to last post
  7. Nested Interrupts and Priorities

    Hi all! I have TFT kit TC297.For the touch controller there is periodic routine and I wanted to call it every 10ms. Thats why I copied simple...

    Started by engineerhan‎, May 27th, 2020 12:37 AM
    • Replies: 4
    • Views: 94
    May 27th, 2020, 07:39 AM Go to last post
  8. AURIX TC387 issues in Port and Mcu Modules in Tersos

    Attached images you can see error: (35016) is appearing consistently : Invalid XPath-expression for Attribute "MIN" of node "PortContainer":...

    Started by yehiahesham‎, May 19th, 2020 07:07 AM
    • Replies: 3
    • Views: 174
    May 26th, 2020, 09:29 AM Go to last post
  9. Erased Flash ECC ( When read by HSM Core), TC399

    I have query regarding 'Reading Erased PFlash by HSM Core' in Aurix TC399 Microcontroller. One of the use case in our product requires that HSM Core...

    Started by umair‎, May 23rd, 2020 02:26 AM
    ecc, exception, hsm, tc399
    • Replies: 1
    • Views: 120
    May 23rd, 2020, 08:22 AM Go to last post
  10. What is the source of SMU ALM8[16] in Aurix 2G?

    Hello Support, What is the source of SMU ALM8 in Aurix 2G? Is it only WDTSSR.TO bit or ALM8 can be due to any other event also? If not, then do we...

    Started by baexps_pr1‎, May 23rd, 2020 02:01 AM
    • Replies: 0
    • Views: 82
    May 23rd, 2020, 02:01 AM Go to last post
  11. TSIM Multiple ELF support / Peripheral simulation

    Hello, I have two questions regarding TSIM : 1. Does TSIM support loading of multiple ELF files ? 2. Where can we find the documentation for...

    Started by Oren‎, May 23rd, 2020 01:08 AM
    • Replies: 0
    • Views: 87
    May 23rd, 2020, 01:08 AM Go to last post
  12. Contentions between CPU vs SRI accesses to PSPR / DSPR

    Hi, After skimming carefully through the datasheet, application notes, and, more generally, the Web... I haven't been able to find any information...

    Started by eric_jenn‎, May 20th, 2020 12:54 AM
    • Replies: 4
    • Views: 170
    May 22nd, 2020, 10:31 AM Go to last post
  13. Is there any other way to execute cyclic interrupts in all three cores? GPT12

    Hi friends, My project need a function like this: an interrupt would be triggered every T seconds. And I need to apply it in all of three...

    Started by valerie‎, May 20th, 2020 05:16 AM
    gpt12, tc277
    • Replies: 2
    • Views: 106
    May 22nd, 2020, 09:17 AM Go to last post
  14. Debug and CPU registers error using DAP IF

    Dear All, I try to FLASHing TC397XE chip using the DAP IF. With DAP telegrams , I can halt main CPU (using the HARR issue). I saw, that corresponds...

    Started by alexeyPhyton‎, May 21st, 2020 08:50 AM
    • Replies: 6
    • Views: 117
    May 22nd, 2020, 07:40 AM Go to last post
  15. Aurix 2G SMU Software Monitor Alarms across multiple CPU Cores and Safety WDT

    Hello Support, In Aurix 2G, there is Software Monitor Alarm possible. There are multiple Software Monitor Alarms which are assigned to different...

    Started by baexps_pr1‎, May 21st, 2020 03:13 PM
    • Replies: 7
    • Views: 113
    May 22nd, 2020, 07:16 AM Go to last post
  16. What is fail action for Core CPU WDT Write from alternate CPU?

    Hello Support, There are 3 Core CPU WDT within Aurix2G. So, Core 0 can write to Core CPU WDT0. Core 1 can write to Core CPU WDT1. ...

    Started by baexps_pr1‎, May 21st, 2020 06:04 PM
    • Replies: 3
    • Views: 82
    May 22nd, 2020, 05:17 AM Go to last post
  17. Is there PLL Range Check possible for Aurix 2G similar to Aurix 1G

    Hello Support, In Aurix 1G, there was PLL output range monitoring as shown below. Is there any way one can implement fPLL0 range monitoring in...

    Started by baexps_pr1‎, May 21st, 2020 08:42 AM
    • Replies: 5
    • Views: 95
    May 21st, 2020, 11:53 AM Go to last post
  18. Autosar for aurix

    Hi, I am working on Autosar, can anyone help me to know which tools to be use to generated code for different layers of Autosar.

    Started by KDN‎, May 21st, 2020 05:53 AM
    aurix
    • Replies: 3
    • Views: 103
    May 21st, 2020, 11:32 AM Go to last post
  19. Does ACCEN Protection applicable for Core WDT in Aurix 2G?

    Hello Support, In the SCU Register set, there is ACCEN00 Register. Does Core CPU WDT access control possible using ACCEN register settings in Aurix...

    Started by baexps_pr1‎, May 21st, 2020 09:36 AM
    • Replies: 1
    • Views: 63
    May 21st, 2020, 10:01 AM Go to last post
  20. TC399 sector erase and write times

    Hi, I would like to understand the erase time and write time of a pfls sector. Where can this data be found?

    Started by kfir‎, May 21st, 2020 06:06 AM
    • Replies: 2
    • Views: 58
    May 21st, 2020, 06:20 AM Go to last post

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