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Meyer
Aug 13th, 2013, 06:15 AM
Hey Infineon-Team and all other ;)

I got a Problem with the Uart Interrupt. It only occurs with even bit values. It is thought that the interrupt occurs for each incoming character. So the letter 'c' is decimal '99' bin: 1100011

4 bits is even and the interrupt occurs. The letter 'a' is decimal '97' bin: 1100001 ; 3 bits is uneven or odd and the interrupt don´t occurs.



void uart_init(const UART001_HandleType* Handle)
{
USIC_CH_TypeDef* UartRegs = Handle->UartRegs;
//Deaktivieren des UART-Modus
UartRegs->CCR &= ~( ((uint32_t)(UART_MODE & USIC_CH_CCR_MODE_Msk)));
// aktivieren des Uart channels ; Mode = 1 BpModen=1
UartRegs->KSCFG |= ((((uint32_t)0x01 & USIC_CH_KSCFG_MODEN_Msk)) | (((uint32_t)0x01 << USIC_CH_KSCFG_BPMODEN_Pos) & USIC_CH_KSCFG_BPMODEN_Msk));
//Fractional Teiler gewählt ;DM = 10
UartRegs->FDR |= (((uint32_t)0x02 << USIC_CH_FDR_DM_Pos) & USIC_CH_FDR_DM_Msk);
// Step value;
UartRegs->FDR |= ((Handle->BGR_STEP) & USIC_CH_FDR_STEP_Msk);

UartRegs->BRG |= ((((uint32_t)(Handle->BGR_PCTQ) << USIC_CH_BRG_PCTQ_Pos) & USIC_CH_BRG_PCTQ_Msk) | \
(((uint32_t)(Handle->BGR_DCTQ) << USIC_CH_BRG_DCTQ_Pos) & USIC_CH_BRG_DCTQ_Msk) | \
(((uint32_t)(Handle->BGR_PDIV) << USIC_CH_BRG_PDIV_Pos) & USIC_CH_BRG_PDIV_Msk));

// PDL = 1; TRm =1
UartRegs->SCTR |= ((((uint32_t)0x01 << USIC_CH_SCTR_PDL_Pos) & USIC_CH_SCTR_PDL_Msk ) | (((uint32_t)0x01 << USIC_CH_SCTR_TRM_Pos ) & USIC_CH_SCTR_TRM_Msk ));
// word length frame length
UartRegs->SCTR |= ((((uint32_t)Handle->DataBits << USIC_CH_SCTR_FLE_Pos) & USIC_CH_SCTR_FLE_Msk ) | \
(((uint32_t)Handle->DataBits << USIC_CH_SCTR_WLE_Pos) & USIC_CH_SCTR_WLE_Msk));

//TBUF Data Enable (TDEN) = 1
//TBUF Data Single Shot Mode (TDSSM) = 1
UartRegs->TCSR |= ((((uint32_t)0x01 << USIC_CH_TCSR_TDEN_Pos) & USIC_CH_TCSR_TDEN_Msk ) | (((uint32_t)0x01 << USIC_CH_TCSR_TDSSM_Pos) & USIC_CH_TCSR_TDSSM_Msk));
//Sample Mode (SMD) = 1
// 1 Stop bit
// Sample Point (SP) as configured
//Pulse Length (PL) = 0
UartRegs->PCR_ASCMode |= ((((uint32_t)0x01 & USIC_CH_PCR_ASCMode_SMD_Msk)) | (((uint32_t)Handle->StopBit << USIC_CH_PCR_ASCMode_STPB_Pos) & \
USIC_CH_PCR_ASCMode_STPB_Msk) | (((uint32_t)(Handle->BGR_SP) << USIC_CH_PCR_ASCMode_SP_Pos) & USIC_CH_PCR_ASCMode_SP_Msk));

if(Handle->RecvNoiseEn)
{
/* Enable Receiver Noise Interrupt*/
UartRegs->PCR_ASCMode |=(((uint32_t)0x01 << USIC_CH_PCR_CTR5_Pos) & USIC_CH_PCR_CTR5_Msk);
}

if(Handle->FormatErrEn)
{
/* Enable Format Error Interrupt*/
UartRegs->PCR_ASCMode |=(((uint32_t)0x01 << USIC_CH_PCR_CTR6_Pos) & USIC_CH_PCR_CTR6_Msk);
}

if(Handle->FrameFinEn)
{
/* Enable Frame Finished Interrupt*/
UartRegs->PCR_ASCMode |=(((uint32_t)0x01 << USIC_CH_PCR_CTR7_Pos) & USIC_CH_PCR_CTR7_Msk);
}
//Configuration of Transmitter Buffer Control Register; Limit = 10
UartRegs->TBCTR |= ((((uint32_t)Handle->TxLimit << USIC_CH_TBCTR_LIMIT_Pos ) & USIC_CH_TBCTR_LIMIT_Msk));
//Configuration of Receive Buffer Control Register; Limit =110; LOf = 1;
UartRegs->RBCTR |= ((((uint32_t)Handle->RxLimit << USIC_CH_RBCTR_LIMIT_Pos) & USIC_CH_RBCTR_LIMIT_Msk) | \
(((uint32_t)0x01 << USIC_CH_RBCTR_LOF_Pos) & USIC_CH_RBCTR_LOF_Msk));

//UartRegs->RBCTR |= (USIC_CH_RBCTR_SRBINP_Msk >> 2 ) & (0x10000);
//UartRegs->RBCTR |= USIC_CH_RBCTR_SRBIEN_Msk;

//parity generation is disabled
UartRegs->CCR |= (((uint32_t)(UART_MODE & USIC_CH_CCR_MODE_Msk)) | \
(((uint32_t)Handle->Parity << USIC_CH_CCR_PM_Pos) & USIC_CH_CCR_PM_Msk));
// Receive Interrupt enable
UartRegs->CCR |= USIC_CH_CCR_RIEN_Msk;
// Interrupt Node pointer register
// SR1 aktiv
UartRegs->INPR|= (USIC_CH_INPR_RINP_Msk >> 1)&(0x100);


}



void UART_INIT_Test(void)
{

NVIC_SetPriority(USIC1_1_IRQn,1); // Priority = 1
NVIC_EnableIRQ(USIC1_1_IRQn);
}



void MyUART_ISR(const UART001_HandleType* Handle,uint16_t* DataPtr)
{
Debug_test->Debug1++;
P1_1_toggle();
}
void USIC1_1_IRQHandler(void)
{
//P1_1_toggle();
MyUART_ISR(&UART001_Handle0,ptr_test);
}

The configuration in the hyperterminal are correct and i don´t know where the mistake is...

Pls help me ;)

Jackson
Aug 13th, 2013, 08:46 PM
Hi Meyer,

Are you referring to Receive Interrupt?
Are you using XMC4500?
If yes, there is hardware bug in USIC causing the calculation of parity bit for UART to be error.
In ASC/UART protocol, if the received data having parity error, Alt. Receive Interrupt is triggered instead of Standard Receive Interrupt.
Because of the HW bug, USIC will trigger the alt. receive interrupt as if the receive data having parity bit error although the parity is correct.
The workaround would be enable both standard receive and alternate receive interrupt and point to the same interrupt handler.
In this case, all incoming data will trigger the interrupt handler.

Meyer
Aug 14th, 2013, 03:05 AM
Are you referring to Receive Interrupt?

Yes


Are you using XMC4500?

YES


there is hardware bug in USIC causing the calculation of parity bit for UART to be error.
In ASC/UART protocol, if the received data having parity error, Alt. Receive Interrupt is triggered instead of Standard Receive Interrupt.
Because of the HW bug, USIC will trigger the alt. receive interrupt as if the receive data having parity bit error although the parity is correct.


Thank u very much ;)