PDA

View Full Version : Time Offset between 2 DMA Transactions via SPI (SSC)



Marco@fs
Jan 10th, 2013, 04:57 AM
hello,

My assignment:

--> SPI Transmit via DMA Transfer with follow settings:

- Blocksize = 8

Source:
- Incerement
- Single Transfer Width = 16
- Burst Width = 4

Destination:
- no change
- Single Transfer Width = 16
- Burst Width = 4

Ther are some time between the two transaction (2*(4*16bit)). Here the SPI Transmit Register (IN[0] loaded twice with 4*16bit))


If have the follow settings, it is all right and the SPI transfers all the data without time delay between!

Destination:
- no change
- Single Transfer Width = 16
- Burst Width = 8

(Here the SPI Transmit Register (IN[0] loaded one time with 8*16bit))

What is the Problem?

attachment:
- osci_print.jpg

Marco@fs
Jan 14th, 2013, 02:34 AM
hello,

i think these issue is handmade from me. This Post is also not longer actual. Sorry thats my mistake...