View Full Version : QSPI Initialization code for TC23x

May 13th, 2015, 08:49 AM
Hello All,
I need Initialization code for QSPI on TC23x. I don't intend to use DMA. I need to communicate with or without Interrupts. Thanks.

May 22nd, 2015, 08:34 AM
Hello Farazo,
Glad to hear that you are using the AURIX and want to get things up and running!

Do you have access to the AURIX documentation, SW Framework, and iLLD on myinfineon.com?

The SW Framework and iLLD have QSPI initialization code which you can use to accomplish your task.

If you need help getting your myinfineon.com account, please let me know.

Carl Bonfiglio
Infineon Marketing Manager

usha cy
Aug 23rd, 2015, 11:21 PM
Hi Do you got any updates on this. Even am looking for this .

Sep 7th, 2015, 07:14 AM
Hope you will find my example helpful.


usha cy
Sep 7th, 2015, 09:44 PM
Thanks for your sample code.. its helped me in better understanding.

Jul 13th, 2019, 11:28 AM
Can anyone help me to understand it.

uint16 endinit_pw = IfxScuWdt_getCpuWatchdogPassword();
((Ifx_QSPI*)spiModule)->CLC.U = 0;
volatile uint32 dummy = ((Ifx_QSPI*)spiModule)->CLC.U;

Jul 13th, 2019, 03:26 PM
When you write to any special function register (SFR) there are write attributes associated with them. For example do you need to be in supervisor or user mode and if it is a critical register it could be CPU or Safety ENDINIT protected.

The CLC register in the QSPI peripheral has the following write attributes (Supervisor mode and it is CPU ENDINIT protected).

The first line gets the current password being used by the CPU.
The second line opens temporary CPU access by this CPU to an ENDINIT (“End of initialization”) protected register
The third line is writing 0 to the QSPI CLC (clock control register) which enables the clock at the peripheral and allow further access to other registers. If the CLC is not enabled for a peripheral you cannot write other registers in that peripheral.
The forth line read back the value from the peripheral, What you need to know is the CPU has a write buffer, and a read from the same location will force the write to occur before the read.
The fifth line closes that temporary CPU access to ENDINIT

Jul 14th, 2019, 10:10 AM
Hi ,

I think only enabling clock do't work, there must be some other setting also. Can you help me to understand that or can you share if you have any document on it.

I have configure QSPI, but not able to see any output on data or clock bus either chip select working.