Digital to anolog Converter xmc4500

[#1]

Hi,

how to generate sine wave in pattern generation mode.

[#2]

Hi Arun,

You can use the DACWG001 Apps in DAVE3 to generate the waveform.

[#3]

Hi,

I also have a question about signal generation with the DAC using the GPDMA.

I would like to generate a continuous periodic signal, say a sine wave. For low frequencies, e.g. 200 Hz, the pattern generator is not really acceptable due to the very low resolution. Now my idea was to store one period of the signal in a lookup table. Let's say I use 8192 entries (12 bit each) and set the DAC to data mode with a trigger frequency of 8192*200=1.64 MHz.
At that rate I'd obviously like to use a DMA channel.

Since the signal shall not exhibit any gaps I must make sure that the rollover from the last entry of the LUT to the first is done in "hardware", i.e. without CPU actions.
Fortunately the GPDMA supports autoreload and linked list operations, albeit only on CH0 and CH1.

First question:
The user manual (XMC4400, Rev 1.4) says:

19.7.2.1 Service Request Connections
Two service requests DAC.SR0 and DAC.SR1 are used for simultaneous and independent data mode. DAC.SR1 can be enabled on DMA channel 2 and DAC.SR0 can be enabled on DMA channel 3.

That would be bad, because those DMA channels do not support the required mode. But within the GPDMA section I read:

4.4.2 DMA Service Request Source Selection
The selection of the request sources is done according to the following table by programming the DLR_SRSEL0 register ...

And there DAC.SR0 is connected to DLR line 1 (page 4-11) which I can connect to GPDMA CH0 or CH1.
At least that is how I interpret GPDMA register "CTL" described on page 5-81. By setting field "DEST_PER" (page 5-84) to 01 the channel is triggered by DLR line 1 requests.

Do I miss something or am I lucky an the manual is wrong and the DAC channels can be actually also serviced by GPDMA channels 0 and 1?

If I'm lucky: I would program GPDMA channel 0 for linked list mode and have a single block linked to itself. I would set source width to 32 bit and destination width to 16 bit. Each LUT entry then contains 12 bits for the DAC within a word (2 bytes).
I hope that a 16 bit write to the DAC data register is sufficient to trigger the conversion?
If so, the maximum block length of 4096 32bit entries is just enough to provide 8192 sample values ...

Best regards,

Mike

[Travis]

Miguel wrote:
Hi,

I also have a question about signal generation with the DAC using the GPDMA.

I would like to generate a continuous periodic signal, say a sine wave. For low frequencies, e.g. 200 Hz, the pattern generator is not really acceptable due to the very low resolution. Now my idea was to store one period of the signal in a lookup table. Let's say I use 8192 entries (12 bit each) and set the DAC to data mode with a trigger frequency of 8192*200=1.64 MHz.
At that rate I'd obviously like to use a DMA channel.

Since the signal shall not exhibit any gaps I must make sure that the rollover from the last entry of the LUT to the first is done in "hardware", i.e. without CPU actions.
Fortunately the GPDMA supports autoreload and linked list operations, albeit only on CH0 and CH1.

First question:
The user manual (XMC4400, Rev 1.4) says:

19.7.2.1 Service Request Connections
Two service requests DAC.SR0 and DAC.SR1 are used for simultaneous and independent data mode. DAC.SR1 can be enabled on DMA channel 2 and DAC.SR0 can be enabled on DMA channel 3.

That would be bad, because those DMA channels do not support the required mode. But within the GPDMA section I read:

4.4.2 DMA Service Request Source Selection
The selection of the request sources is done according to the following table by programming the DLR_SRSEL0 register ...

And there DAC.SR0 is connected to DLR line 1 (page 4-11) which I can connect to GPDMA CH0 or CH1.
At least that is how I interpret GPDMA register "CTL" described on page 5-81. By setting field "DEST_PER" (page 5-84) to 01 the channel is triggered by DLR line 1 requests.

Do I miss something or am I lucky an the manual is wrong and the DAC channels can be actually also serviced by GPDMA channels 0 and 1?

If I'm lucky: I would program GPDMA channel 0 for linked list mode and have a single block linked to itself. I would set source width to 32 bit and destination width to 16 bit. Each LUT entry then contains 12 bits for the DAC within a word (2 bytes).
I hope that a 16 bit write to the DAC data register is sufficient to trigger the conversion?
If so, the maximum block length of 4096 32bit entries is just enough to provide 8192 sample values ...

Best regards,

Mike

Hi Mike,

It is not a matter of lucky, but it is a fact that DMA CH2 and CH3 does not support link list. :0)

I was wondering if you can accept a minor CPU intervention to increment the Source address (Look up table) using a DMA interrupt.

1) DAC.SR0 >> 2) Start DMA CH3 transfer >> 3) DMA interrupt >> 4) Increment source address >> Repeat from 1

[#5]

Hi Travis,

> It is not a matter of lucky, but it is a fact that DMA CH2 and CH3 does not support link list. :0)

yes, this I know. And indeed, if I have to use CH2 or CH3 then I will try to use a scheme like the one you have outlined.
I had even thought of using the ERU to create more linked list channels (a second DMA reloading the registers of the first after the block transfer end of the first).
The register layout would have been well suited for that, since the registers to be reloaded occupy a contiguous address space.
But alas the DMA end of block signal goes to the NVIC only, not to the ERU.

The primary question is, however, is it really true that DAC.SR0 is linked to CH3 only?
I simply fail to see this restriction.

Assume I program register GPDMA0_CH0_CFGH with 0x01 in the DEST_PER field.
I also would clear bit HS_SEL_DST and set bit HS_SEL_SRC in register GPDMA0_CH0_CFGL.
Then, according to the reference manual XMC4400, V1.4, channel 0 of GPDMA0 should use DLR line 1 as a trigger source.
Now I program the field RS1 in register DLR_SRSEL0 to 0x5. This should select DAC.SR0 as the request source for DLR line 1.

So after that the DAC0 should be linked to CH0 of the GPDMA0: DAC.SR0 -> DLR1 -> GPDMA0.CH0

Do I miss something? I'm new to XMC family and maybe I have a black out, but where would be the error in the setup?
(I cannot try on actual HW at this moment.)

Best regards,

Mike

[Travis]

Hi Mike,

>The primary question is, however, is it really true that DAC.SR0 is linked to CH3 only?

The individual DMA channel has got the flexibility to select which DLR connection by setting the SRC_PER bit field. (See attachment)



DAC.SR0 is hardwired to the DLR line 1, 5, 8 and 10 (4.4.2 DMA Service Request Source Selection). Hence you have to enable one of them. eg. DLS_SRSEL.RS1 = 0101 for DLR 1.



> Assume I program register GPDMA0_CH0_CFGH with 0x01 in the DEST_PER field.
> I also would clear bit HS_SEL_DST and set bit HS_SEL_SRC in register GPDMA0_CH0_CFGL.
You are setting hardware handshaking for both source and destination.

> Then, according to the reference manual XMC4400, V1.4, channel 0 of GPDMA0 should use DLR line 1 as a trigger source.
> Now I program the field RS1 in register DLR_SRSEL0 to 0x5. This should select DAC.SR0 as the request source for DLR line 1.
This is correct, after this point you have to link you DMA channel to the desire DLR by setting GPDMA0_CH0_CFGH.SRC_PER

I hope you can understand the inter connection of the DMA.

Best Regards
Travis

[#7]

Travis wrote:
Hi Mike,

>The primary question is, however, is it really true that DAC.SR0 is linked to CH3 only?

The individual DMA channel has got the flexibility to select which DLR connection by setting the SRC_PER bit field. (See attachment)

DAC.SR0 is hardwired to the DLR line 1, 5, 8 and 10 (4.4.2 DMA Service Request Source Selection). Hence you have to enable one of them. eg. DLS_SRSEL.RS1 = 0101 for DLR 1.

Yes, but this same selection is also provided for CH0 and CH1, see page 5-81:

And so we both agree that one can link DAC.SR0 to any DMA channel, not only to CH3, OK?
That's fine with me, because then the user manual for the XMC has ist wrong:

"19.7.2.1 Service Request Connections
Two service requests DAC.SR0 and DAC.SR1 are used for simultaneous and
independent data mode. DAC.SR1 can be enabled on DMA channel 2 and DAC.SR0
can be enabled on DMA channel 3."

So the XMC is more flexible than the user manual admits and I can use channel linking - perfect.

Travis wrote:

> Assume I program register GPDMA0_CH0_CFGH with 0x01 in the DEST_PER field.
> I also would clear bit HS_SEL_DST and set bit HS_SEL_SRC in register GPDMA0_CH0_CFGL.
You are setting hardware handshaking for both source and destination.

Why is that? If I set the SRC bit (i.e. HS_SEL_SRC = 1) then I thought it's SW handshake?

My idea is to feed the DAC via DMA from an array. The samples shall go to the DAC at regular intervals, so I would let the DAC trigger the DMA.

DAC: dst, hence HW handshake for DST
MEM: src, hence no HW handshake for SRC


Best regards,

Mike

[Travis]

Hi Mike,

There are some DAVE example regarding DMA + DAC which might suit your needs.

http://www.infineon.com/cms/en/product/promopages/aim-mc/dave_downloads.html

Do a search on "DMA"

Sine wave generation with DACWG002 and DMA
This example project uses the DACWG002 App and DMA App. It create a sine waveform using the DMA to transfer the waveform points from memory to DAC Data Registers. It shows how to change the frequency, offset and scale of the generated waveform at runtime. The output signal can be seen on Pin 14.9 .


Sine wave generation with DACWG002 and DMA DACWG002_DMA002_Example2
This example project uses the DACWG002 App and DMA App. It create a sine waveform using the DMA to transfer the waveform points from memory to DAC Data Registers. It shows how to change the frequency, offset and scale of the generated waveform at runtime. The output signal can be seen on Pin 14.9 .

Sine wave generation with DACWG003 and DMA DACWG003 App Example:
This Example Generates two Sine Waveforms using DMA. The DMA is used to transfer the Waveform points from Memory to DAC Data Registers. It shows how to change the frequency, offset and Scale of the Generated Sine waveform at runtime.

Sine wave generation with DMA and DACWG002 DACWG002_DMA002_Example2
This example project uses the DACWG002 App and DMA App. It create a sine waveform using the DMA to transfer the waveform points from memory to DAC Data Registers. It shows how to change the frequency, offset and scale of the generated waveform at runtime. The output signal can be seen on Pin 14.9 .

[#9]

Thanks for the Apps!
I tried one and it works as expected. I checked and in my case the app used DAC1 and GPDMA.CH0.
Perfect, shows that one can link the DACs to the linked list capable channels. I also checked the settings of the DLR registers and the GPDMA0.CH0 registers and so far all bits were set as I would have expected. Also fine, because I don't want to use the APP as is and therefore have to understand the manual for manual settings 🙂

I suggest someone removes the misleading statement in the user manual that says that the DACs "can be linked to CH2/CH3".
They surely "can" be linked to CH2/3 also, but as it is one would think that they are fixed to CH2/3.
Yet they can be linked to any CHx, at least of GPDMA0.


Thanks again for your time!

Mike

[User16641]

Hey Mike,

I have a similar Problem to solve.
I would like to build a Connection between DMA and DAC unfortunately it doesn´t work.
I want to use the XMC-4700.
But it should be similar to your Project.

Could you help me?

It would be nice to post a little Abstract of your Code?

Best regards,

Matix