Parity Error checking feature is offered for
- PSAM
- DSRAM
- USIC memory
- MCAN memory
- USB memory
- ETH memory
- SDMMC memory
This can be enable through the "PEEN" (Parity Errror Enable Register)
Do note that there are TWO modes of parity error signalling:
- bus error (applies to memories that can be accessed directly from the bus system level eg. DSRAM)
- parity error trap (applies to memories that are internal to peripherals eg. USIC, MCAN, USB)
Parity trap requests get enabled with PETE register implementing individual control for each memory. Parity error trap generation mechanism can be also used to generate System Reset if enabled with PERSTEN register in conjunction with the PETE register configuration.
